Datasheet

PN512 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 5.2 — 16 June 2016
111352 116 of 137
NXP Semiconductors
PN512
Full NFC Forum-compliant frontend
[1] The voltage on pin RX is clamped by internal diodes to pins AVSS and AVDD.
[2] I
pd
is the total current for all supplies.
[3] I
DD(PVDD)
depends on the overall load at the digital pins.
[4] I
DD(TVDD)
depends on V
DD(TVDD)
and the external circuit connected to pins TX1 and TX2.
[5] During typical circuit operation, the overall current is below 100 mA.
[6] Typical value using a complementary driver configuration and an antenna matched to 40  between pins TX1 and TX2 at 13.56 MHz.
[7] I
DD(SVDD)
depends on the load at pin MFOUT.
I
pd
power-down current V
DDA
=V
DDD
= V
DD(TVDD)
=
V
DD(PVDD)
=3V
hard power-down; pin
NRSTPD set LOW
[2]
--15A
soft power-down; RF
level detector on
[2]
--30A
Clock frequency
f
clk
clock frequency - 27.12 - MHz

clk
clock duty cycle 40 50 60 %
t
jit
jitter time RMS - - 10 ps
Crystal oscillator
V
OH
HIGH-level output voltage pin OSCOUT - 1.1 - V
V
OL
LOW-level output voltage pin OSCOUT - 0.2 - V
C
i
input capacitance pin OSCOUT - 2 - pF
pin OSCIN - 2 - pF
Typical input requirements
f
xtal
crystal frequency - 27.12 - MHz
ESR equivalent series resistance - - 100 
C
L
load capacitance - 10 - pF
P
xtal
crystal power dissipation - 50 100 W
Table 169. Characteristics
…continued
Symbol Parameter Conditions Min Typ Max Unit