Datasheet

PN512 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 5.2 — 16 June 2016
111352 110 of 137
NXP Semiconductors
PN512
Full NFC Forum-compliant frontend
Especially when using time slot protocols, it is needed that the error flag is copied into the
status information of the frame. When using the RxMultiple feature (see Section 8.2.2.4
on page 39) within version 1.0 the protocol error flag is not included in the status
information for the frame. In addition the CRCOk is copied instead of the CRCErr. This
can be a problem in frames without length information e.g. ISO/IEC 14443-B.
The version 1.0 does not accept a Type B EOF if there is no 1 bit after the series of 0 bits,
as such the configuration within Section 8.2.2.15 “
TypeBReg” on page 50 bit 4 for
RxEOFReq does not exist. In addition the IC only has the possibility to select the
minimum or maximum timings for SOF/EOF generation defined in ISO/IEC14443B. As
such the configuration possible in version 2.0 through the EOFSOFAdjust bit (see Section
8.2.4.7 “AutoTestReg” on page 64) does not exist and the configuration is limited to only
setting minimum and maximum length according ISO/IEC 14443-B, see Section 8.2.2.15
“TypeBReg” on page 50, bit 4.
21. Application design-in information
The figure below shows a typical circuit diagram, using a complementary antenna
connection to the PN512.
The antenna tuning and RF part matching is described in the application note “NFC
Transmission Module Antenna and RF Design Guide”.
Fig 38. Typical circuit diagram
AVDD TVDD
RX
VMID
supply
TX1
TVSS
TX2
DVSS
DVDD
DVDD
PVDD
SVDD
AVSS
IRQ
NRSTPD
R
1
R
2
L
0
C
0
C
0
C
2
C
1
C
RX
R
Q
R
Q
C
1
C
2
L
0
C
vmid
001aan232
27.12 MHz
OSCIN OSCOUT
HOST
CONTROLLER
interface
PN512
antenna
Lant