Datasheet

PN512 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 5.2 — 16 June 2016
111352 11 of 137
NXP Semiconductors
PN512
Full NFC Forum-compliant frontend
Table 4. Pin description HVQFN40
Pin Symbol Type Description
1 to 4 A2 to A5 I Address Line
5 PVDD PWR Pad power supply
6DVDDPWRDigital Power Supply
7 DVSS PWR Digital Ground
8 PVSS PWR Pad power supply ground
9 NRSTPD I Not Reset and Power Down: When LOW, internal current sinks are switched off, the
oscillator is inhibited, and the input pads are disconnected from the outside world. With
a positive edge on this pin the internal reset phase starts.
10 SIGIN I Communication Interface Input: accepts a digital, serial data stream
11 SIGOUT O Communication Interface Output: delivers a serial data stream
12 SVDD PWR S
2
C Pad Power Supply: provides power to the S
2
C pads
13 TVSS PWR Transmitter Ground: supplies the output stage of TX1 and TX2
14 TX1 O Transmitter 1: delivers the modulated 13.56 MHz energy carrier
15 TVDD PWR Transmitter Power Supply: supplies the output stage of TX1 and TX2
16 TX2 O Transmitter 2: delivers the modulated 13.56 MHz energy carrier
17 TVSS PWR Transmitter Ground: supplies the output stage of TX1 and TX2
18 AVDD PWR Analog Power Supply
19 VMID PWR Internal Reference Voltage: This pin delivers the internal reference voltage.
20 RX I Receiver Input
21 AVSS PWR Analog Ground
22 AUX1 O Auxiliary Outputs: These pins are used for testing.
23 AUX2 O
24 OSCIN I Crystal Oscillator Input: input to the inverting amplifier of the oscillator. This pin is
also the input for an externally generated clock (f
osc
= 27.12 MHz).
25 OSCOUT O Crystal Oscillator Output: Output of the inverting amplifier of the oscillator.
26 IRQ O Interrupt Request: output to signal an interrupt event
27 NWR I Not Write: strobe to write data (applied on D0 to D7) into the PN512 register
28 NRD I Not Read: strobe to read data from the PN512 register (applied on D0 to D7)
29 ALE I Address Latch Enable: signal to latch AD0 to AD5 into the internal address latch
when HIGH.
30 NCS I Not Chip Select: selects and activates the host controller interface of the PN512
31 to 38 D0 to D7 I/O 8-bit Bi-directional Data Bus.
Remark: For serial interfaces this pins can be used for test signals or I/Os.
Remark: If the host controller selects I
2
C as digital host controller interface, these pins
can be used to define the I
2
C address.
39 to 40 A0 to A1 I Address Line