Specifications

Appendix A—Code Examples
SPRZ293A—November 2009 TMS320C6457 Fixed-Point Digital Signal Processor Silicon Errata 43
www.ti.com
Submit Documentation Feedback Silicon Revisions 1.0, 1.1, 1.2, 1.3, 1.4 .
Long Distance Load Word Routine ldld.asm
;; ======================================================================== ;;
;; Long Distance Load Word ;;
;; ;;
;; int long_dist_load_word(volatile int *addr) ;;
;; ;;
;; This function reads a single word from a remote location with the L1D ;;
;; cache frozen. This prevents L1D from sending victims in response to ;;
;; these reads, thus preventing the L1D victim lock from engaging for the ;;
;; corresponding L1D set. ;;
;; ;;
;; The code below does the following: ;;
;; ;;
;; 1. Disable interrupts ;;
;; 2. Freeze L1D ;;
;; 3. Load the requested word ;;
;; 4. Unfreeze L1D ;;
;; 5. Restore interrupts ;;
;; ;;
;; Interrupts are disabled while the cache is frozen to prevent affecting ;;
;; the performance of interrupt handlers. Disabling interrupts during ;;
;; the long distance load does not greatly impact interrupt latency, ;;
;; because the CPU already cannot service interrupts when it's stalled by ;;
;; the cache. This function adds a small amount of overhead (~20 cycles) ;;
;; to that operation. ;;
;; ;;
;; ======================================================================== ;;
.asg 0x01840044, L1DCC ; L1D Cache Control
.global _long_dist_load_word
.text
.asmfunc
; int long_dist_load_word(volatile int *addr)
_long_dist_load_word:
MVKL L1DCC, B4
MVKH L1DCC, B4
|| DINT ; Disable interrupts
|| MVK 1, B5
STW B5, *B4 ; \_ Freeze cache
LDW *B4, B5 ; /
NOP 4
SHR B5, 16, B5 ; POPER -> OPER
|| LDW *A4, A4 ; read value remotely
NOP 4
STW B5, *B4 ; \_ Restore cache
RET B3
|| LDW *B4, B5 ; /
NOP 4
RINT ; Restore interrupts
.endasmfunc
;; ======================================================================== ;;
;; End of file: ldld.asm ;;
;; ======================================================================== ;;