Specifications

Appendix A—Code Examples
SPRZ293A—November 2009 TMS320C6457 Fixed-Point Digital Signal Processor Silicon Errata 41
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L1D Block Writeback-Invalidate Routine l1d_block_wbinv.asm
;; ======================================================================== ;;
;; L1D Block Writeback-Invalidate ;;
;; ;;
;; l1d_block_wbinv(void *base, size_t byte_count); ;;
;; ;;
;; Performs a block writeback-invalidate from L1D to L2. It can be used ;;
;; on any address range (L2 or external), but it only operates on L1D ;;
;; cache. ;;
;; ;;
;; Maximum block size is 256K. Exact maximum byte count depends on the ;;
;; alignment of the block. ;;
;; ;;
;; Interrupts are disabled during the block writeback operation. ;;
;; ======================================================================== ;;
.asg 0x01844030, L1DWI ; L1D Block Wb-Inv; BAR at 0, WC at 1
.global _l1d_block_wbinv
.text
.asmfunc
_l1d_block_wbinv:
MVC DNUM, B0 ; \_ Get global alias prefix
ADDK 0x10, B0 ; /
SHRU A4, 24, B2 ; Get prefix from address
CMPEQ B0, B2, B0 ; Check if address prefix is global
[ B0] EXTU A4, 8, 8, A4 ; Remove global prefix from address
MVKL L1DWI, B6 ;
CLR A4, 0, 5, A1 ; Align to L1D cache line boundary
|| ADD A4, B4, B1 ; Compute end of buffer
ADDK 63, B1 ; \_ Round to next L1D cache line
CLR B1, 0, 5, B1 ; /
SUB B1, A1, B1 ; Count cache-line span in bytes
|| MVKH L1DWI, B6 ;
SHR B1, 2, B1 ; Convert to "word count"
|| DINT ; Disable interrupts
STW A1, *B6[0] ; Store base address
STW B1, *B6[1] ; Store word count
; Note: The following loop is intentionally low-rate to avoid
; interfering with the block writeback operation.
loop: LDW *B6[1], B1 ; Read remaining word-count
NOP 4
[ B1] BNOP loop, 5 ; Loop until done
RINT ; Reenable interrupts
RETNOP B3, 5 ; Return to caller
.endasmfunc
;; ======================================================================== ;;
;; End of file: l1d_block_wbinv.asm ;;
;; ======================================================================== ;;