Specifications

Silicon Updates
SPRZ293A—November 2009 TMS320C6457 Fixed-Point Digital Signal Processor Silicon Errata 39
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Submit Documentation Feedback Silicon Revisions 1.0, 1.1, 1.2, 1.3, 1.4 .
Usage Note 1 Manual Cache Coherence Operation Usage Note
Revision(s) Affected: 1.3, 1.2, 1.1, 1.0
Details: When an L1DWB, L1DWBINV, L2DWB, or L2DWBINV command is executed, and
the writeback is complete, the C64x+ Megamodule will send a single 128-bit message
with the address of the last word that the block operation was for. On OMAP devices,
the extra sideband signal mentioned above is used to route that to a special endpoint.
On the HPMP devices, TI did not hook up this signal and therefore this looks like any
other write command.
Because CPU to CPU transfers are not allowed in the connectivity of the SCR, the
address is treated as an invalid address and the command is immediately terminated at
the null-endpoint within the SCR and goes nowhere. There should be no effect at all to
the system by this behavior.
Workaround 1: No workaround is available as there is no effect on the system by this behavior.