Specifications

38 TMS320C6457 Fixed-Point Digital Signal Processor Silicon Errata SPRZ293A—November 2009
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Silicon Revisions 1.0, 1.1, 1.2, 1.3, 1.4 Submit Documentation Feedback
Workaround 1: Leave in previous SDMA/IDMA stall workarounds (for devices with the original
SDMA/IDMA stall).
For silicon versions 1.0, 1.1, and 1,2 that were already affected with the first
SDMA/IDMA stall issue from Advisory 9, there is no additional workaround needed.
If all of the deadlock avoidance steps listed in Advisory 9 have been followed, there is
no risk for a deadlock because of this issue. Methods to reduce stalling due to this issue
are also already covered in advisory Advisory 9.
For silicon version 1.3 that fixed the initial condition of SDMA/IDMA stall issue, the
deadlock avoidance steps that are already listed in Advisory 9 for previous revisions of
silicon should be followed to ensure there is no chance of a deadlock. The workarounds
to avoid stalls are also the same as communicated in previous revisions of the device
with the issue.
Workaround 2: Do not place program code in external memory.
This issue can be avoided by either ensuring that all program code is in L1P or L2
SRAM or SL2 SRAM. This eliminates the possibility of creating an L1P$ miss that
generates an L2 read from external memory.
Workaround 3: Allocate all CPU writeable DMA buffers/variables in UMAP0 or L1D RAM.
Note—DMA in this case refers to EDMA and other masters external to the
C64x+ megamodule.
If possible, move DMA buffers that are also writeable by the CPU to completely reside
in UMAP0 or L1D RAM. This prevents SDMA traffic to multiple UMAP ports.
Workaround 4: Allocate CPU Data Buffers/Variables in UMAP0.
If possible, move CPU data buffers/variables out of UMAP1 to UMAP0. This
eliminates the CPU data accesses to/from UMAP1. Please see ‘‘Appendix C—UMAP0
and UMAP1 Addresses Ranges’’.
Workaround 5: Allocate CPU-readable Data Buffers/Variables in UMAP1.
Note—Because the L2$ is located in UMAP0, this workaround assumes that
L2$ is disabled.
If possible, move CPU-readable data buffers/variables out of UMAP0 to UMAP1. This
eliminates the CPU data reads from UMAP0. CPU writes are to UMAP1 are OK.
Again, please see ‘‘Appendix C—UMAP0 and UMAP1 Addresses Ranges’’.