Specifications

Silicon Updates
SPRZ293A—November 2009 TMS320C6457 Fixed-Point Digital Signal Processor Silicon Errata 37
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The SDMA in item 1 sets up a bank conflict for the L1D$ read in item 2. The L1D$
allocate in item 2 prevents the L1D$ write/victim (3) from advancing, so it is stuck in
the pipeline. This occurs at the same time as an L1P$ allocate that also results in an L2
access to external memory (4), which is also in the same pipeline stage as the L1D$
write/victim (3). At this point, the L1P$ allocate (4) advances to the next pipeline stage
but the L1D$ write/victim (3) is still stuck waiting on the L1D$ allocate (2). This now
sets up the pipeline for the stall condition, which is actually triggered by an SDMA to
UMAP1 (5). This is what causes further SDMAs to stall. After the L1P$ allocate (4) is
complete, (2) resolves, allowing (3) to resolve thus freeing the SDMA pipeline again.
Therefore, the stall is effectively for the length of the L1P$ allocate in item (4).
Please note that the above four conditions do not guarantee that a stall will occur, it may
stall depending on the timing between the transactions. Steps 2 and 3 must occur
within two CPU cycles of each other and steps 3 and 4 must occur within five CPU
cycles of each other.
Figure 6 shows this timing relationship.
Figure 6 L2 P1 CMD Pipe – Time Progression
SDMA
to UMP0
L1D Read Miss
UMAP0
L1D WB (or) VCT
L1P Miss,
L2$ Miss
SDMA UMAP1
SDMA Stalled
SDMA in FSM
L2 WB/VCT in FSM
L2 RD Miss in FSM
2 Cycles Between These Two Events
5 Cycles Between These Two Events
L2 P1 CMD Pipe -- Time Progression