Specifications

36 TMS320C6457 Fixed-Point Digital Signal Processor Silicon Errata SPRZ293A—November 2009
Silicon Updates
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Silicon Revisions 1.0, 1.1, 1.2, 1.3, 1.4 Submit Documentation Feedback
Advisory 10 L1P$ Miss May Block SDMA Accesses (Asymmetric Mode Only)
Revision(s) Affected: 1.3, 1.2, 1.1, 1.0
Details: This advisory is an update to Advisory 9 in this document. Advisory 9 lists the
following blocking condition:
• Stall Condition 1 - L2 victim traffic due to L2 block writeback during any pending
CPU request
This advisory covers one more blocking condition:
• Stall Condition 2 - L1P$ miss may stall SDMA accesses
For silicon versions 1.0, 1.1, and 1.2 that contain the original SDMA/IDMA blocking
advisory, this is a second way to hit the SDMA/IDMA stall in addition to the previously
communicated errata conditions in Advisory 9.
No additional deadlock risk potential is created by the addition of the new bug to
silicon 1.0, 1.1, and 1.2 that currently contain the first SDMA/IDMA blocking
condition (described in Advisory 9). That means that this new issue can lead to a
deadlock in the same manner that the other condition can. On silicon revision 1.3
without the original stall condition, this creates a deadlock condition that is identical to
the previous revisions.
Under certain conditions, L2 accesses to external memory resulting from an L1P$ miss
can block SDMA/IDMA accesses during CPU/DMA requests. There are several
transactions that must happen to cause an SDMA/IDMA to stall because of this
condition:
1. A DMA access to UMAP0
2. An L1D$ read miss from UMAP0
1
3. An L1D$ write or victim to UMAP1. This happens as a result of one of the
following:
– An L1D victim (through L1D writeback or writeback-invalidate) to UMAP1
– An L1D read+victim (through L1D read miss resulting in a writeback) to any
L2
2
– An L1D write miss (write-through to an uncached line)
4. An L1P$ miss that results in an L2 access to external memory. L2 victim can
create deadlock or preceding long distance write.
3
5. An SDMA access to UMAP
4, 5
Table 9 C6457 Silicon Revisions and SDMA/IDMA Stall Conditions
Silicon Revision Stall Condition 1 Stall Condition 2
Rev 1.2 and earlier YES YES
Rev 1.3 NO YES
Rev 1.4 NO NO
End of Table 9
1.Note that if SW is currently running in L1D$ Freeze Mode during this transaction, transaction 1 is not needed to reproduce this issue.
2.The victim generated still needs to go to UMAP1. The reason that the L1D$ read can be to any L2 address (UMAP0 or UMAP1) is that there is no way of knowing if the least
recently used cache line that will be evicted is in UMAP0 or UMA1.
3.This step may not be necessary if a long distance write to external memory is currently pending.
4.It is also important to note that without step 5, this issue does not exist. That means that if the resolution of the pipeline is completed before (5), then the issue is not seen.
5.If an SDMA access to UMAP0 occurs before transaction (5), the pipeline is flushed and this issue is not seen.