Specifications

Silicon Updates
SPRZ293A—November 2009 TMS320C6457 Fixed-Point Digital Signal Processor Silicon Errata 35
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› Re-block the loops. In some cases, restructuring loops can increase reuse
in the cache and reduce the total traffic to external memory.
› Throttle the loops. If restructuring the code is impractical, then it is
reasonable to slow it down. This reduces the likelihood that consecutive
SDMA/IDMA blocks stack up in the cache request pipelines, resulting in
a long stall.
– Protect non-cacheable reads from generating an SDMA stall by freezing the
L1D cache during the non-cacheable read access(es).
› The long_dist_load_word function (please see the code listing for
ldld.asm provided in section of Appendix A—Code Examples) is
suitable for isolated accesses, contains a function that protects
non-cacheable reads, avoids blocking during the reads, and, therefore,
avoids the deadlock state.
Workaround 3: Entirely eliminate the exception by removing all SDMA/IDMA accesses to L2 SRAM.
For example, EMAC descriptors and EMAC payload cannot reside in L2. Master
peripherals like the EDMA/QDMA, IDMA, and SRIO cannot access L2. There are no
issues with the CPU itself accessing code/data in L2. This issue only pertains to
SDMA/IDMA accesses to L2.
Deadlock Avoidance
To avoid the manifestation of a C64x+ deadlock, several workarounds: are suggested
depending on the VBUSM master in question (Table 8):
Table 8 VBUSM Masters and Associated Workarounds
VBUSM Master Workaround
EDMA3TCx Inbound and outbound traffic should be programmed on different TC ports (i.e. two
different EDMA queues, because a given queue maps to a given TC). Note that
in-/out-bound direction is defined as the write direction, meaning that a DDR2-to-DDR2
transfer is outbound and L2-to-L2 is inbound. Any TC used to write to DDR should not be
used to write to a megamodule even when the TC writing to the DDR is also reading
from DDR.
EMAC EMAC should write to the megamodule's memory or the DDR, but not both. This
includes buffers and buffer descriptors. EMAC CPPI descriptors should be placed entirely
in the local wrapper memory, any combination of wrapper and L2 memory (must match
other master transactions), or any combination of wrapper and DDR2 SDRAM (must
match other master transactions). Buffer descriptors should not be placed in any
combination of L2 and DDR2 SDRAM.
SRIO SRIO should transfer payload data only to megamodule memories or to DDR2 SDRAM,
but not both. This includes any direct I/O writes as well as any inbound RX messaging
transfer.
SRIO CPPI SRIO CPPI descriptors should be placed entirely in the local wrapper memory, any
combination of wrapper and L2 memory, or any combination of wrapper and DDR2
SDRAM. Buffer descriptors should not be placed in any combination of L2 and
DDR2 SDRAM.
End of Table 8