Specifications

Silicon Updates
SPRZ293A—November 2009 TMS320C6457 Fixed-Point Digital Signal Processor Silicon Errata 33
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Submit Documentation Feedback Silicon Revisions 1.0, 1.1, 1.2, 1.3, 1.4 .
Details: Under certain conditions, L2 victim traffic due to a block writeback can block
SDMA/IDMA accesses to UMAP0 during CPU requests. For a definition of UMAP0
for the C6457 device, see ‘‘Appendix C—UMAP0 and UMAP1 Addresses Ranges’’.
There are four transactions that must occur to cause an SDMA/IDMA to stall because
of this condition:
1. L1D/L1P needs to create an L2$ hit. This happens as a result of one of the
following:
– An L1D victim (through L1D writeback or writeback-invalidate)
– An L1D read+victim (through L1D read miss resulting in a writeback)
– An L1D write miss (write-through to an uncached line)
– An L1D read miss
– An L1P fetch miss
2. A user-initiated L2 block writeback must occur involving the same cache set as
the previous L2$ hit.
3. An SDMA access to UMAP0
4. The CPU also accesses the same cache set as the previous 2 bullets. This happens
as a result of a CPU LDx/STx instruction that causes one of the following:
– • An L1D victim (through L1D writeback or writeback-invalidate)
– • An L1D write miss (write-through to an uncached line)
– • An L1D read miss
– • An L1P fetch miss
As a result of the four steps above, any further SDMA to UMAP0 are blocked. SDMA
to UMAP1 are unaffected. Again, note that the three of these items MUST involve the
same L2$ set in order to see the issue and thus is not as likely as the other conditions
listed in the original errata. The stall will persist until the operations above are
complete.
Workaround 1: As mentioned in the background material above, issues such as dropped McBSP
samples can be worked around by moving latency-sensitive buffers outside the C64x+
megamodule. For example, rather than placing buffers for the McBSP into L1/L2, those
buffers can instead be placed in other memory, such as the EMAC CPPI RAM.
Note—The EMAC CPPI RAM memory is word-addressable only and,
therefore, must be accessed using an EDMA index of 4 bytes.