Specifications

Silicon Updates
SPRZ293A—November 2009 TMS320C6457 Fixed-Point Digital Signal Processor Silicon Errata 31
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Submit Documentation Feedback Silicon Revisions 1.0, 1.1, 1.2, 1.3, 1.4 .
Figure 5 is a simplified view for illustrative purposes only. The IDMA/SDMA path
(orange lines) can also go to L1D/L1P memories and IDMA can go to the DSP CFG
peripherals. MDMA transactions (blue lines) can also originate from L1P or L1D
through the L2 controller or directly from the DSP.
Figure 5 IDMA, SDMA, and MDMA Paths
The duration of the SDMA/IDMA stalls depend on the quantity/characteristics of the
L1/L2 cache and the MDMA traffic in the system. Therefore, it is difficult to predict if
stalling will occur and for how long.
Cache Control
Memory Protect
Bandwidth Mgmt
L1P
RAM/
Cache
256
Bandwidth Mgmt
Memory Protect
Cache Control
256
L2
256
RAM/
Cache
ROM
256
Instruction Fetch
C64x + CPU
256
Cache Control
Memory Protect
Bandwidth Mgmt
L1D
64 64
8x32
256
256
256
CFG
MDMA SDMA
EMC
256
32
Peripherals
128
128
RAM/
Cache
Register
File A
Register
File B
EDMA Master
Peripherals
IDMA
128
Power Down
Interrupt
Controller
CPU/Cache Access Origination
Master Peripheral Origination