Specifications

30 TMS320C6457 Fixed-Point Digital Signal Processor Silicon Errata SPRZ293A—November 2009
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Advisory 9 L2 Victim Traffic Due To L2 Block Writeback During Any Pending CPU
Request
Revision(s) Affected: 1.2, 1.1, 1.0
Background: The C64x+ megamodule has a Master Direct Memory Access (MDMA) bus interface
and a Slave Direct Memory Access (SDMA) bus interface. The MDMA interface
provides DSP access to resources outside the C64x+ megamodule (i.e., DDR2
memory). The MDMA interface is used for CPU/cache accesses to memory beyond the
level 2 (L2) memory level. These accesses include cache line allocates, write-backs, and
non-cacheable loads and stores to/from system memories. The SDMA interface allows
other master peripherals in the system to access level 1 data (L1D), level 1 program
(L1P), and L2 RAM DSP memories. The masters allowed accesses to these memories
are DMA controllers, EMAC, and SRIO. The DSP Internal Direct Memory Access
(IDMA) is a C64x+ megamodule DMA engine used to move data between internal DSP
memories (L1, L2) and/or the DSP peripheral configuration bus. The IDMA engine
shares resources with the SDMA interface.
The C64x+ megamodule has an L1D cache and an L2 cache, both of which implement
write-back data caches. The C64x+ megamodule holds updated values for external
memory as long as possible. It writes these updated values, called victims, to external
memory when it needs to make room for new data, when requested to do so by the
application, or when a load is performed from a non-cacheable memory for which
there is a set match in the cache (i.e., the non-cacheable line would replace a dirty line
if cached). The L1D sends its victims to L2. The caching architecture has pipelining,
meaning multiple requests could be pending between L1, L2, and MDMA. For more
details on the C64x+ megamodule and its MDMA and SDMA ports, see the
TMS320C64x+ Megamodule Reference Guide (literature number SPRU871).
Figure 5 shows IDMA, SDMA, and MDMA paths. Ideally, the MDMA (the blue lines)
and SDMA/IDMA paths (the orange lines) operate independently with minimal
interference. Normally, MDMA accesses may stall for extended periods of time (clock
cycles) due to expected system level delays (e.g., bandwidth limitations, DDR2 memory
refreshes).
However, when using L2 as RAM, SDMA, and/or IDMA accesses to L2/L1 may
experience unexpected stalling in addition to the normal stalls seen by the MDMA
interface. For latency-sensitive traffic, the SDMA stall can result in missing real-time
deadlines.
Note—SDMA/IDMA accesses to L1P/D will not experience an unexpected
stall if there are no SDMA/IDMA accesses to L2. Unexpected SDMA/IDMA
stalls to L1 happen only when they are pipelined behind L2 accesses.