Specifications

Silicon Updates
SPRZ293A—November 2009 TMS320C6457 Fixed-Point Digital Signal Processor Silicon Errata 29
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Submit Documentation Feedback Silicon Revisions 1.0, 1.1, 1.2, 1.3, 1.4 .
Workaround 3: Workaround for Buffers that the CPU and DMA Access Asynchronously
While this situation is rare in most programs, there are some cases where both the CPU
and the DMA access the same structure without explicit synchronization. In some
cases, this is due to the fact that said accesses are part of an algorithm that implements
a synchronization primitive. Regardless of the purpose, these accesses potentially
trigger this bug.
The easiest way to avoid the bug with this case is to freeze the L1D whenever the CPU
reads this buffer. This prevents the buffer from allocating in the L1D cache so that the
DMA never sends a snoop (read or write) to the DMC on behalf of this buffer.
Alternately, programs can always invalidate the line in L1D after reading it so that all
writes to the line miss L1D and the line is never present and dirty in L1D cache.
Programs can use the L1D block invalidate (L1DIBAR/L1DIWC) or L1D block
writeback-invalidate (L1DWIBAR/L1DWIWC) to perform these explicit coherence
operations.