Specifications

Silicon Updates
SPRZ293A—November 2009 TMS320C6457 Fixed-Point Digital Signal Processor Silicon Errata 25
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Figure 3 shows the sequence of events.
Figure 3 Sequence of Events
Table 7 shows the expected data values after this sequence completes and the actual
values that are now present because of this issue.
.
Incorrect Order
Correct Order
UMAPx
SRAM
t2
Dirty
Corruption
L1D
t0
t1
t3’
DMA Write
(Snoop Write)
CPU Read
(L2 Cache)
t4
t3
t0: CPU Allocate
t1: Victim Start
t2: Allocation Data
t3: DMA Write (SNPW)
t4: Victim Done
t0: CPU Allocate
t1: Victim Start
t2: Allocation Data
t4: DMA Write (SNPW)
t3: Victim Done
Table 7 Expected vs. Actual Data Values
1
1. Key:
A, B = Original Data
A’ = CPU-written data
A’’, B’’ = DMA-written data
A’’’ = CPU-and-DMA-written data, properly merged
Buffer Expected Actual
Buffer A A’’’ B’’
Buffer B B’’ B
End of Table 7