Specifications

24 TMS320C6457 Fixed-Point Digital Signal Processor Silicon Errata SPRZ293A—November 2009
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The following steps must all occur concurrently to see the issue:
1. The CPU reads from any address in L2 SRAM that is a set match to Cache Line A
(to determine if a set match condition exists, see Appendix B—Determining If
Two Addresses are a Set Match)
– The set match to Cache Line A is referred to here as Cache Line B.
– This results in a cache miss from the CPU and sends a read request to L2
cache for the line (and possibly an external source if it was through L2 cache
or if no L2 cache is present).
– Because Cache Line A is dirty, a victim is prepared to be sent after Cache Line
B is allocated and is held in a temporary victim data buffer
› Please see Appendix B—Determining If Two Addresses are a Set Match
for instructions on how to determine if two addresses are a set match.
2. The DMA read or writes from/to Cache Line A, mentioned in the prerequisite
above. This means that it is not necessarily the same exact address, but within the
same 64B cache line.
– As a result, a snoop-read/-write request is generated.
3. The DMA writes to Cache Line B, mentioned in Step 1. This means that it is not
necessarily the same exact address, but within the same 64B cache line as Step 1.
– As a result, a snoop-write request is generated but not immediately issued, as
it is blocked by the snoop-read/-write issued in Step 2.
The results of the above cause the following to occur:
• The L1D controller receives the new line (B) back from the L2 Controller.
• If Step 2 above was a write, the snoop-write to Cache Line A updates the victim
buffer correctly. If it was a read, the snoop-read returned the correct data to the
DMA.
• The snoop-write to Cache Line B (Step 3 above) incorrectly updates the victim
buffer instead of the newly allocated line that was returned in Step A.
As a result, the following is true:
1. Cache Line A now holds data that was corrupted by Steps 3 and C above.
– subsequent read of this data returns a corrupted value.
2. Cache Line B now holds stale data, as it was never updated with the data it was
supposed to get from Steps 3 and C.
– The CPU gets stale data (not updated).
Corruption happens only when the DMA accesses an L1D cache line that the CPU also
writes to. This results in DMAs that may match victim lines leaving L1D. Thus, it can
affect buffers that the CPU fills with writes and the DMA reads, as well as buffers where
both the DMA and CPU write. It does not affect DMA buffers that the CPU only reads.