Specifications

22 TMS320C6457 Fixed-Point Digital Signal Processor Silicon Errata SPRZ293A—November 2009
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Workaround 4: Allocate DMA Buffers in L1D RAM or UMAP0
If possible, move DMA buffers that the CPU reads directly out of UMAP1 to either
UMAP0 or L1D RAM. A table showing UMAP0 addresses of the C6457 can be found
in Table 6. DMA buffers that the CPU does not access directly can remain in UMAP1
safely, as these will not generate snoops.
If the user’s set of in-bound DMA buffers does not fit in L1D RAM and UMAP0
statically, consider paging buffers from UMAP1 to either UMAP0 or L1D RAM. That
is, allow DMA to write to buffers in UMAP1 freely, but never read them directly from
the CPU. Instead, use IDMA to copy a buffer from UMAP 1 to either UMAP0 or L1D
RAM before using it.
The IDMA1 utility functions (please see the code listing for idma1_util.asm
provided in the section of Appendix A—Code Examples) can be used for copying data
with the IDMA controller.
Table 6 UMAP0 Address Range for C6457
UMAP0 Address Range
1
1. Please note that L2 cache, if used, is a portion of the address range.
RAM 0x00900000 - 0x009FFFFF
End of Table 6