Specifications

Silicon Updates
SPRZ293A—November 2009 TMS320C6457 Fixed-Point Digital Signal Processor Silicon Errata 19
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Submit Documentation Feedback Silicon Revisions 1.0, 1.1, 1.2, 1.3, 1.4 .
Figure 2 shows the flow of these operations, the incorrect order that causes the issue,
and the correct order to avoid the issue. The solid line is Cache Line A and the dashed
line is Cache Line B.
Figure 2 Cache Line Operations Flow
All of the conditions described above must be true to see the issue. The workarounds
focus on picking one of the conditions and removing it so that the user does not need
to worry about the other condition.
TI proposes starting with workaround 1 as an immediate fix. The other workarounds
that follow may provide a solution with reduced overhead and/or simplified
implementation depending on the system scenario.
Workaround 1: Write Back and Invalidate DMA Buffers
L1D corruption occurs when DMA writes to a buffer in UMAP1 that is also cached
in L1D, at the same time the L1D is discarding the buffer. Thus, this affects buffers
where the DMA writes, and the CPU reads. It does NOT affect buffers that the CPU
only writes and/or the DMA only reads.
t0: DMA Write
t1: CPU Allocate
t2: Allocation Data
t3: Snoop Write
t0: DMA Write
t1: CPU Allocate
t2: Snoop Write
t0: Allocation Data
Incorrect Order Correct Order
UMAP0 UMAP1
External
Buffer
t2
Clean
Corruption
L1D
t0
t1
t3
DMA Write
(Snoop Write)
CPU Read
(L2 Cache)
Cache Line ACache Line B