Specifications

18 TMS320C6457 Fixed-Point Digital Signal Processor Silicon Errata SPRZ293A—November 2009
Silicon Updates
www.ti.com
Silicon Revisions 1.0, 1.1, 1.2, 1.3, 1.4 Submit Documentation Feedback
3. The CPU reads from a cacheable, external memory (e.g., DDR) that is a set match
to Cache Line A (referred to here as Cache Line B). Determining if two addresses
are a set match can be done by comparing certain bits of two addresses. The
mapping of an address to a location in L1D cache is shown in Figure 7.
– Please see Appendix B—Determining If Two Addresses are a Set Match for
instructions on how to determine of two addresses are a set-match.
This results in a cache miss from the CPU for an external address and sends a read
request to L2 cache for the line (and possibly to the external source on an L2 cache miss
or if no L2 cache is present).
The results of the above cause the following to occur:
• L2 sends both the return data for the L1D read miss request (response of Step 3
above) and the data for the snoop-write (response of Step 2 above). The L1D
commits the snoop-write data after the L2 return data.
• As a result, L1D now holds the wrong data for the external address (Cache Line
B) and commits the data to cache. Cache Line B remains marked clean. If the
program does not write to the uncorrupted portion of the line and does not read
the corrupted portion of the line, the corruption goes unnoticed. If the program
writes to the uncorrupted portion of the line, the corrupted data gets written back
to L2 cache and/or external memory. Otherwise, the corruption disappears when
L1D discards the line.
• Cache lines holding external addresses are the only cache lines that exhibit
corruption. Corruption happens only when DMA buffers in UMAP1 get cached
in L1D. In addition, corruption happens only when the DMA buffer is clean,
meaning that it gets discarded without generating a victim. Thus, this affects
buffers where the DMA writes and the CPU reads. It does not affect buffers that
the CPU only writes and/or DMA only reads.
One can identify this bug unambiguously by examining the corrupted memory range
in CCStudio using the cache tag viewer. The corrupted data shows up in the include
L1D view in a memory window, but not in the exclude L1D view. The cache tag viewer
should indicate that the line is also clean and the corrupt data should also be visible in
its intended destination, which must be in UMAP1 and map to the same L1D set as the
corrupted line.