Specifications

16 TMS320C6457 Fixed-Point Digital Signal Processor Silicon Errata SPRZ293A—November 2009
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busy every cycle. Hence, the DMAs stall until the stream of CPU accesses completes.
For example, if a continuous stream of L1D write misses to L2 keep the L2 memory
controller busy every cycle, the DMAs stall for the entire duration of the write miss
stream.
Note—When the SDMA has finished sending all of its commands to the L2
controller the C64x+ Megamodule drops the effective transfer priority down to
7 if no further commands are in the pipeline. This condition happens when
there is a single word access, a burst of less than 32B with no other SDMA
commands pending, or for only the last 64B of a burst that is greater than 64B
with no other SDMA commands pending. This effective priority level is what
the L2 controller uses to arbitrate these SDMA commands with the CPU,
irrespective of what the actual programmed priority value is of the master
peripheral. This means that if the CPU is programmed to priority 7, via the
CPUARB register, this issue will be triggered. Therefore, priority 7 is not a
valid priority level for CPU. If for any reason this demoted transfer is still
pending upon initiation of another transfer, it will automatically inherit the
priority of that new transfer and be pushed through such that it does not stall
the new transfer.
Workaround 1: Set the CPU and the DMA commands to L2 on different priorities. As noted above,
Priority 7 is not a valid priority for the CPU.