User manual

Raisecom Technology Co., Ltd
14
SET TS16 TS17 TS18 TS19 TS20 TS21 TS22 TS23
ON √ √ √ √ √ √ √ √
OFF × × × × × × × ×
SW4 definition (default is all OFF)
1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit
SET TS24 TS25 TS26 TS27 TS28 TS29 TS30 TS31
ON √ √ √ √ √ √ √ √
OFF × × × × × × × ×
Notice:
When the SW1-1 is OFF (unframed mode) the TS1 to TS31 is invalid.
When the SW1-1 is ON( Fractional mode) the TS1 to TS31 bits are valid and can not
be all OFF. That is to say there must be some timeslot which is enabled.
4.3.2. Function Dip-switch (SW5)
In below table “√” indicates enable; “×” indicates disable
Definition of SW5 (The 1
st
and 2
nd
bits are ON in default and others are OFF)
1
st
bit 2
nd
bit 3
rd
bit 4
th
bit 5
th
bit 6
th
bit 7
th
bit 8
th
bit
Set
Timing1
Clock
1
st
Timing2
Clock
2
nd
TS_FLOW
Timeslot
Follow
BET
Error
Code
Test
RX CLK
Phase
LP_EN
Two
direction
loop back
LP_SEL
Loop back
position
Reserved
N/A
ON * * √ √ Reverse √ Local -
OFF * * × × Positive × Remote Normal
1. The 1
st
and 2
nd
bit: Clock mode choosing dip-switch Timing1, Timing2 (default is
ON)
The Clock mode is defined by the 1
st
bit and 2
nd
bit of SW5, detail is shown in below table:
SW5-1 SW5-2 Clock Mode
OFF OFF Master Clock (Internal clock)
OFF ON
ON OFF
V.35 terminal Clock ( Follow V.35 interface
clock)
ON ON Slave Clock ( Follow fiber line clock)
2. The 3
rd
bit: Timeslot auto follow function TS_FLOW (default OFF)
SW5-3 Timeslot auto follow function
ON Enable