Instruction Manual
Preliminary W79E8213/W79E8213R Data Sheet 
Publication Release Date: July 11, 2008 
- 58 -  Revision A2 
12.2  Priority Level Structure 
The W79E8213 series uses a four priority level interrupt structure (highest, high, low and lowest) and 
supports up to 10 interrupt sources. The interrupt sources can be individually set to either high or low 
levels. Naturally, a higher priority interrupt cannot be interrupted by a lower priority interrupt. However 
there exists a pre-defined hierarchy amongst the interrupts themselves. This hierarchy comes into play 
when the interrupt controller has to resolve simultaneous requests having the same priority level. This 
hierarchy is defined as table below. This allows great flexibility in controlling and handling many 
interrupt sources. 
PRIORITY BITS 
IPXH IPX 
INTERRUPT PRIORITY LEVEL 
0  0  Level 0 (lowest priority) 
0 1 Level 1 
1 0 Level 2 
1  1  Level 3 (highest priority) 
Table 12-2: Four-level interrupt priority 
Each interrupt source can be individually programmed to one of four priority levels by setting or 
clearing bits in the IP0, IP0H, IP1, and IP1H registers. An interrupt service routine in progress can be 
interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority. The 
highest priority interrupt service cannot be interrupted by any other interrupt source. So, if two 
requests of different priority levels are received simultaneously, the request of higher priority level is 
serviced. 
If requests of the same priority level are received simultaneously, an internal polling sequence 
determines which request is serviced. This is called the arbitration ranking. Note that the arbitration 
ranking is only used to resolve simultaneous requests of the same priority level. 
As below Table summarizes the interrupt sources, flag bits, vector addresses, enable bits, priority bits, 
arbitration ranking, and whether each interrupt may wake up the CPU from Power-down mode. 
Source Flag 
Vector 
address 
Interrupt 
Enable Bits
Interrupt 
Priority 
Flag 
cleared by
Arbitration 
Ranking 
Power- 
Down 
Wakeup
External 
Interrupt 0 
IE0  0003H  EX0 (IE0.0)  IP0H.0, IP0.0
Hardware, 
Follow the 
inverse of pin
1(highest) Yes 
Brownout 
Detect 
BOF  002BH  EBO (IE.5)  IP0H.5, IP0.5
Software 
2 Yes 
Watchdog Timer  WDIF  0053H  EWDI (EIE.4) IP1H.4, IP1.4
Software 
3 No 
Timer 0 
Interrupt 
TF0  000BH  ET0 (IE.1)  IP0H.1, IP0.1
Hardware, 
software 
4 No 










