Instruction Manual

Preliminary W79E8213/W79E8213R Data Sheet
Publication Release Date: July 11, 2008
- 40 - Revision A2
BIT NAME FUNCTION
7
PED
1: To set interrupt priority of Edge Detect is higher priority level.
6
PPWM
1: To set interrupt priority of PWM underflow is higher priority level.
5
PBK
1: To set interrupt priority of PWM’s external brake is higher priority level.
4
PWDI
1: To set interrupt priority of Watchdog is higher priority level.
3-0
-
Reserved.
BUZZER CONTROL REGISTER
Bit: 7 6 5 4 3 2 1 0
- - BUZDIV.5 BUZDIV.4 BUZDIV.3 BUZDIV.2 BUZDIV.1 BUZDIV.0
Mnemonic: BUZCON Address: F9h
BIT NAME FUNCTION
7-6
-
Reserved.
5-0
BUZDIV
Buzzer division select bits:
These bits are division selector. User may configure these bits to further divide
the cpu clock in order to generate the desired buzzer output frequency.
The following shows the equation for the buzzer output rate;
Fbuz = Fcpu x 1/[(256)x(BUZDIV + 1)]