Manual

ManualsBrandsRainbow Electronics ManualsStorageW25Q32

W25Q80, W25Q16, W25Q32

Advanced Information

Publication Release Date: June 20, 2007

- 1 - Advanced - Revision A5

8M-BIT, 16M-BIT AND 32M-BIT

SERIAL FLASH MEMORY WITH

DUAL AND QUAD SPI

Summary of content (60 pages)

PAGE 1
W25Q80, W25Q16, W25Q32 Advanced Information 8M-BIT, 16M-BIT AND 32M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI -1- Publication Release Date: June 20, 2007 Advanced - Revision A5
PAGE 2
W25Q80, W25Q16, W25Q32 Table of Contents 1. GENERAL DESCRIPTION ......................................................................................................... 5 2. FEATURES ................................................................................................................................. 5 3. PIN CONFIGURATION SOIC 208-MIL....................................................................................... 6 4. PIN CONFIGURATION WSON 6X5-MM .................................
PAGE 3
W25Q80, W25Q16, W25Q32 11. 12. 10.2.4 Write Enable (06h)........................................................................................................21 10.2.5 Write Disable (04h).......................................................................................................21 10.2.6 Read Status Register-1 (05h) and Read Status Register-2 (35h).................................22 10.2.7 Write Status Register (01h) ....................................................................
PAGE 4
W25Q80, W25Q16, W25Q32 12.2 8-Pin PDIP 300-mil (Package Code DA) ...................................................................... 54 12.3 8-contact 6x5 WSON .................................................................................................... 55 12.4 8-contact 6x5 WSON Cont’d. ....................................................................................... 56 12.5 16-Pin SOIC 300-mil (Winbond Package Code SF)..................................................... 57 13.
PAGE 5
W25Q80, W25Q16, W25Q32 1. GENERAL DESCRIPTION The W25Q80 (8M-bit), W25Q16 (16M-bit), and W25Q32 (32M-bit) Serial Flash memories provide a storage solution for systems with limited space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP) and storing voice, text and data. The devices operate on a single 2.7V to 3.
PAGE 6
W25Q80, W25Q16, W25Q32 3. PIN CONFIGURATION SOIC 208-MIL Figure 1a. W25Q80, W25Q16, W25Q32 Pin Assignments, 8-pin SOIC 208-mil (Package Code SS) 4. PAD CONFIGURATION WSON 6X5-MM Figure 1b. W25Q80, W25Q16 Pad Assignments, 8-pad WSON (Package Code ZP) 5. PIN DESCRIPTION SOIC 208-MIL, AND WSON 6X5-MM PIN NO.
PAGE 7
W25Q80, W25Q16, W25Q32 6. PIN CONFIGURATION SOIC 300-MIL Figure 1c. W25Q16 and W25Q32 Pin Assignments, 16-pin SOIC 300-mil (Package Code SF) 7. PIN DESCRIPTION SOIC 300-MIL PAD NO.
PAGE 8
W25Q80, W25Q16, W25Q32 7.1 Package Types W25Q80 is offered in an 8-pin plastic 208-mil width SOIC (package code SS) and 6x5-mm WSON (package code ZP). W25Q16 is offered in an 8-pin plastic 208-mil width SOIC (package code SS) and 6x5-mm WSON as shown in figure 1a, and 1b, respectively. The W25Q16 and W25Q32 are offered in a 16-pin plastic 300-mil width SOIC (package code SF) as shown in figure 1c. Package diagrams and dimensions are illustrated at the end of this datasheet. 7.
PAGE 9
W25Q80, W25Q16, W25Q32 8. BLOCK DIAGRAM Figure 2.
PAGE 10
W25Q80, W25Q16, W25Q32 9. FUNCTIONAL DESCRIPTION 9.1 SPI OPERATIONS 9.1.1 Standard SPI Instructions The W25Q80/16/32 is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK), Chip Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI instructions use the DI input pin to serially write instructions, addresses or data to the device on the rising edge of CLK. The DO output pin is used to read data or status from the device on the falling edge CLK.
PAGE 11
W25Q80, W25Q16, W25Q32 /HOLD condition will terminate after the next falling edge of CLK. During a /HOLD condition, the Serial Data Output (DO) is high impedance, and Serial Data Input (DI) and Serial Clock (CLK) are ignored. The Chip Select (/CS) signal should be kept active (low) for the full duration of the /HOLD operation to avoid resetting the internal logic state of the device. 9.
PAGE 12
W25Q80, W25Q16, W25Q32 10. CONTROL AND STATUS REGISTERS The Read Status Register-1 and Status Register-2 instructions can be used to provide status on the availability of the Flash memory array, if the device is write enabled or disabled, the state of write protection and the Quad SPI setting. The Write Status Register instruction can be used to configure the devices write protection features and Quad SPI setting.
PAGE 13
W25Q80, W25Q16, W25Q32 10.1.6 Status Register Protect (SRP1, SRP0) The Status Register Protect bits (SRP1 and SRP0) are non-volatile read/write bits in the status register (S8 and S7). The SRP bits control the method of write protection: software protection, hardware protection, power supply lock-down or one time programmable (OTP) protection. SRP1 SRP0 /WP Status Register Description 0 0 X Software Protection /WP pin has no control.
PAGE 14
W25Q80, W25Q16, W25Q32 Figure 3a. Status Register-1 Figure 3b.
PAGE 15
W25Q80, W25Q16, W25Q32 10.1.
PAGE 16
W25Q80, W25Q16, W25Q32 STATUS REGISTER(1) W25Q16 (16M-BIT) MEMORY PROTECTION SEC TB BP2 BP1 BP0 BLOCK(S) ADDRESSES DENSITY PORTION X X 0 0 0 NONE NONE NONE NONE 0 0 0 0 1 31 1F0000h - 1FFFFFh 64KB Upper 1/32 0 0 0 1 0 30 and 31 1E0000h - 1FFFFFh 128KB Upper 1/16 0 0 0 1 1 28 thru 31 1C0000h - 1FFFFFh 256KB Upper 1/8 0 0 1 0 0 24 thru 31 180000h - 1FFFFFh 512KB Upper 1/4 0 0 1 0 1 16 thru 31 100000h - 1FFFFFh 1MB Upper 1/2 0 1 0 0 1 0 00
PAGE 17
W25Q80, W25Q16, W25Q32 STATUS REGISTER(1) W25Q80 (8M-BIT) MEMORY PROTECTION SEC TB BP2 BP1 BP0 BLOCK(S) ADDRESSES DENSITY PORTION X X 0 0 0 NONE NONE NONE NONE 0 0 0 0 1 15 0F0000h - 0FFFFFh 64KB Upper 1/16 0 0 0 1 0 14 and 15 0E0000h - 0FFFFFh 128KB Upper 1/8 0 0 0 1 1 12 thru 15 0C0000h - 0FFFFFh 256KB Upper 1/4 0 0 1 0 0 8 thru 15 080000h - 0FFFFFh 512KB Upper 1/2 0 1 0 0 1 0 000000h - 00FFFFh 64KB Lower 1/16 0 1 0 1 0 0 and 1 000000
PAGE 18
W25Q80, W25Q16, W25Q32 10.2 INSTRUCTIONS The instruction set of the W25Q80/16/32 consists of fifteen basic instructions that are fully controlled through the SPI bus (see Instruction Set table). Instructions are initiated with the falling edge of Chip Select (/CS). The first byte of data clocked into the DI input provides the instruction code. Data on the DI input is sampled on the rising edge of clock with most significant bit (MSB) first.
PAGE 19
W25Q80, W25Q16, W25Q32 10.2.
PAGE 20
W25Q80, W25Q16, W25Q32 10.2.
PAGE 21
W25Q80, W25Q16, W25Q32 10.2.4 Write Enable (06h) The Write Enable instruction (Figure 4) sets the Write Enable Latch (WEL) bit in the Status Register to a 1. The WEL bit must be set prior to every Page Program, Sector Erase, Block Erase, Chip Erase and Write Status Register instruction. The Write Enable instruction is entered by driving /CS low, shifting the instruction code “06h” into the Data Input (DI) pin on the rising edge of CLK, and then driving /CS high. Figure 4.
PAGE 22
W25Q80, W25Q16, W25Q32 10.2.6 Read Status Register-1 (05h) and Read Status Register-2 (35h) The Read Status Register instructions allow the 8-bit Status Registers to be read. The instruction is entered by driving /CS low and shifting the instruction code “05h” for Status Register-1 and “35h” for Status Register-2 into the DI pin on the rising edge of CLK. The status register bits are then shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first as shown in figure 6.
PAGE 23
W25Q80, W25Q16, W25Q32 10.2.7 Write Status Register (01h) The Write Status Register instruction allows the Status Register to be written. A Write Enable instruction must previously have been executed for the device to accept the Write Status Register Instruction (Status Register bit WEL must equal 1). Once write enabled, the instruction is entered by driving /CS low, sending the instruction code “01h”, and then writing the status register data byte as illustrated in figure 7.
PAGE 24
W25Q80, W25Q16, W25Q32 10.2.8 Read Data (03h) The Read Data instruction allows one more data bytes to be sequentially read from the memory. The instruction is initiated by driving the /CS pin low and then shifting the instruction code “03h” followed by a 24-bit address (A23-A0) into the DI pin. The code and address bits are latched on the rising edge of the CLK pin.
PAGE 25
W25Q80, W25Q16, W25Q32 10.2.9 Fast Read (0Bh) The Fast Read instruction is similar to the Read Data instruction except that it can operate at the highest possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight “dummy” clocks after the 24-bit address as shown in figure 9. The dummy clocks allow the devices internal circuits additional time for setting up the initial address. During the dummy clocks the data value on the DO pin is a “don’t care”. Figure 9.
PAGE 26
W25Q80, W25Q16, W25Q32 10.2.10 Fast Read Dual Output (3Bh) The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh) instruction except that data is output on two pins; IO0 and IO1. This allows data to be transferred from the W25Q80/16/32 at twice the rate of standard SPI devices. The Fast Read Dual Output instruction is ideal for quickly downloading code from Flash to RAM upon power-up or for applications that cache codesegments to RAM for execution.
PAGE 27
W25Q80, W25Q16, W25Q32 10.2.11 Fast Read Quad Output (6Bh) The Fast Read Quad Output (6Bh) instruction is similar to the Fast Read Dual Output (3Bh) instruction except that data is output on four pins, IO0, IO1, IO2, and IO3. A Quad enable of Status Register-2 must be executed before the device will accept the Fast Read Quad Output Instruction (Status Register bit QE must equal 1).
PAGE 28
W25Q80, W25Q16, W25Q32 10.2.12 Fast Read Dual I/O (BBh) The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO pins, IO0 and IO1. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to input the Address bits (A23-0) two bits per clock. This reduced instruction overhead may allow for code execution (XIP) directly from the Dual SPI in some applications.
PAGE 29
W25Q80, W25Q16, W25Q32 Figure 12b.
PAGE 30
W25Q80, W25Q16, W25Q32 10.2.13 Fast Read Quad I/O (EBh) The Fast Read Quad I/O (EBh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except that address and data bits are input and output through four pins IO0, IO1, IO2 and IO3 and four Dummy clock are required prior to the data output. The Quad I/O dramatically reduces instruction overhead allowing faster random access for code execution (XIP) directly from the Quad SPI.
PAGE 31
W25Q80, W25Q16, W25Q32 Figure 13b.
PAGE 32
W25Q80, W25Q16, W25Q32 10.2.14 Page Program (02h) The Page Program instruction allows from one byte to 256 bytes (a page) of data to be programmed at previously erased (FFh) memory locations. A Write Enable instruction must be executed before the device will accept the Page Program Instruction (Status Register bit WEL= 1). The instruction is initiated by driving the /CS pin low then shifting the instruction code “02h” followed by a 24-bit address (A23-A0) and at least one data byte, into the DI pin.
PAGE 33
W25Q80, W25Q16, W25Q32 10.2.15 Quad Input Page Program (32h) The Quad Page Program instruction allows up to 256 bytes of data to be programmed at previously erased (FFh) memory locations using four pins: IO0, IO1, IO2, and IO3. The Quad Page Program can improve performance for PROM Programmer and applications that have slow clock speeds <5MHz.
PAGE 34
W25Q80, W25Q16, W25Q32 10.2.16 Sector Erase (20h) The Sector Erase instruction sets all memory within a specified sector (4K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Sector Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “20h” followed a 24-bit sector address (A23-A0) (see Figure 2).
PAGE 35
W25Q80, W25Q16, W25Q32 10.2.17 32KB Block Erase (52h) The Block Erase instruction sets all memory within a specified block (32K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “52h” followed a 24-bit block address (A23-A0) (see Figure 2).
PAGE 36
W25Q80, W25Q16, W25Q32 10.2.18 64KB Block Erase (D8h) The Block Erase instruction sets all memory within a specified block (64K-bytes) to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “D8h” followed a 24-bit block address (A23-A0) (see Figure 2).
PAGE 37
W25Q80, W25Q16, W25Q32 10.2.19 Chip Erase (C7h / 60h) The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Chip Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code “C7h” or “60h”. The Chip Erase instruction sequence is shown in figure 19.
PAGE 38
W25Q80, W25Q16, W25Q32 10.2.20 Erase Suspend (75h) The Erase Suspend instruction “75h”, allows the system to interrupt a sector or block erase operation and then read from or program data to, any other sector or block. The Write Status Register instruction (01h) and Erase instructions (20h, 52h, D8, C7h, 60h ) are not allowed during suspend. Erase Suspend is valid only during the sector or block erase operation. If written during the chip erase or program operation, the Erase Suspend instruction is ignored.
PAGE 39
W25Q80, W25Q16, W25Q32 10.2.22 Power-down (B9h) Although the standby current during normal operation is relatively low, standby current can be further reduced with the Power-down instruction. The lower power consumption makes the Power-down instruction especially useful for battery powered applications (See ICC1 and ICC2 in AC Characteristics). The instruction is initiated by driving the /CS pin low and shifting the instruction code “B9h” as shown in figure 22.
PAGE 40
W25Q80, W25Q16, W25Q32 10.2.23 High Performance Mode (A3h) The High Performance Mode (HPM) instruction must be executed prior to Dual or Quad I/O instructions when operating at high frequencies (see FR and FR1 in AC Electrical Characteristics). This instruction allows pre-charging of internal charge pumps so the voltages required for accessing the Flash memory array are readily available. The instruction sequence includes the A3h instruction code followed by three dummy clocks not shown in Fig. 23.
PAGE 41
W25Q80, W25Q16, W25Q32 When used to release the device from the power-down state and obtain the Device ID, the instruction is the same as previously described, and shown in figure 25, except that after /CS is driven high it must remain high for a time duration of tRES2 (See AC Characteristics). After this time duration the device will resume normal operation and other instructions will be accepted.
PAGE 42
W25Q80, W25Q16, W25Q32 10.2.25 Read Manufacturer / Device ID (90h) The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-down / Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID. The Read Manufacturer/Device ID instruction is very similar to the Release from Power-down / Device ID instruction.
PAGE 43
W25Q80, W25Q16, W25Q32 10.2.26 Read Unique ID Number The Read Unique ID Number instruction accesses a factory-set read-only 64-bit number that is unique to each W25Q80, W25Q16 or W25Q64 device. The ID number can be used in conjunction with user software methods to help prevent copying or cloning of a system. The Read Unique ID instruction is initiated by driving the /CS pin low and shifting the instruction code “4Bh” followed by a four bytes of dummy clocks.
PAGE 44
W25Q80, W25Q16, W25Q32 10.2.27 JEDEC ID (9Fh) For compatibility reasons, the W25Q80/16/32 provides several instructions to electronically determine the identity of the device. The Read JEDEC ID instruction is compatible with the JEDEC standard for SPI compatible serial memories that was adopted in 2003. The instruction is initiated by driving the /CS pin low and shifting the instruction code “9Fh”.
PAGE 45
W25Q80, W25Q16, W25Q32 10.2.28 Mode Bit Reset (FFh) For Fast Read Dual/Quad I/O operations, Mode Bits (M7-0) are implemented to further reduce instruction overhead. By setting the Mode Bits (M7-0) to “Ax” hex, the next Fast Read Dual/Quad I/O operation does not require the BBh/EBh instruction code (See 10.2.12 Fast Read Dual I/O and 10.2.13 Fast Read Quad I/O for detail descriptions).
PAGE 46
W25Q80, W25Q16, W25Q32 11. ELECTRICAL CHARACTERISTICS (PRELIMINARY) (4) 11.1 Absolute Maximum Ratings (1) PARAMETERS SYMBOL Supply Voltage VCC Voltage Applied to Any Pin VIO Transient Voltage on any Pin VIOT Storage Temperature TSTG Lead Temperature TLEAD Electrostatic Discharge Voltage VESD CONDITIONS RANGE UNIT –0.6 to +4.0 V Relative to Ground –0.6 to VCC +0.4 V <20nS Transient Relative to Ground –2.0V to VCC+2.
PAGE 47
W25Q80, W25Q16, W25Q32 11.3 Endurance and Data Retention PARAMETER CONDITIONS MIN Erase/Program Cycles 4KB sector, 32/64KB block or full chip. 100,000 Data Retention MAX UNIT cycles Full Temperature Range 20 years 11.4 Power-up Timing and Write Inhibit Threshold PARAMETER SPEC SYMBOL MIN UNIT MAX VCC (min) to /CS Low tVSL(1) 10 Time Delay Before Write Instruction tPUW 1 10 ms Write Inhibit Threshold Voltage VWI 1 2 V (1) (1) µs Note: 1.
PAGE 48
W25Q80, W25Q16, W25Q32 11.5 DC Electrical Characteristics PARAMETER SYMBOL SPEC CONDITIONS MIN Input Capacitance CIN(1) Output Capacitance Cout(1) Input Leakage TYP VIN = 0V(2) UNIT MAX 6 Pf 8 Pf ILI ±2 µA I/O Leakage ILO ±2 µA Standby Current ICC1 /CS = VCC, VIN = GND or VCC 25 50 µA Power-down Current ICC2 /CS = VCC, VIN = GND or VCC 1 5 µA High performance current ICC3 After enable High Performance mode 50 100 µA Current Read Data / Dual /Quad 1MHz(2) ICC4 C = 0.
PAGE 49
W25Q80, W25Q16, W25Q32 11.6 AC Measurement Conditions PARAMETER SPEC SYMBOL MIN Load Capacitance Input Rise and Fall Times Input Pulse Voltages Input Timing Reference Voltages Output Timing Reference Voltages UNIT MAX CL 30 pF TR, TF 5 ns VIN 0.2 VCC to 0.8 VCC V IN 0.3 VCC to 0.7 VCC V OUT 0.5 VCC to 0.5 VCC V Note: 1. Output Hi-Z is defined as the point where data out is no longer driven. Figure 31.
PAGE 50
W25Q80, W25Q16, W25Q32 11.7 AC Electrical Characteristics SPEC DESCRIPTION SYMBOL ALT UNIT MIN Clock frequency for all instructions, except Read Data (03h) 2.7V-3.6V VCC & Industrial Temperature FR Clock freq. Read Data instruction (03h) fC TYP MAX D.C. 80 MHz fR D.C. 50 MHz Clock High, Low Time except Read Data (03h) tCLH, tCLL(1) 6/7 ns Clock High, Low Time for Read Data (03h) instruction tCRLH, tCRLL(1) 8 ns Clock Rise Time peak to peak tCLCH(2) 0.
PAGE 51
W25Q80, W25Q16, W25Q32 11.
PAGE 52
W25Q80, W25Q16, W25Q32 11.9 Serial Output Timing 11.10 Input Timing 11.
PAGE 53
W25Q80, W25Q16, W25Q32 12. PACKAGE SPECIFICATION 12.1 8-Pin SOIC 208-mil (Package Code SS) SYMBOL A A1 A2 b C D E E1 e L θ y MILLIMETERS MIN MAX 1.75 2.16 0.05 0.25 1.70 1.91 0.35 0.48 0.19 0.25 5.18 5.38 7.70 8.10 5.18 5.38 1.27 BSC 0.50 0.80 0o 8o --0.10 INCHES MIN MAX 0.069 0.085 0.002 0.010 0.067 0.075 0.014 0.019 0.007 0.010 0.204 0.212 0.303 0.319 0.204 0.212 0.050 BSC 0.020 0.031 0o 8o --0.004 Notes: 1. Controlling dimensions: inches, unless otherwise specified. 2.
PAGE 54
W25Q80, W25Q16, W25Q32 12.2 8-Pin PDIP 300-mil (Package Code DA) D 8 5 E1 4 1 B B 1 E S c A1 A A2 Base Plane Seating Plane L e1 α Symbol A A1 A2 B B1 c D E E1 e1 L α eA S Dimension in inch Min Nom Max Dimension in mm Min Nom 0.010 Max 4.45 0.175 0.25 0.125 0.130 0.135 3.18 3.30 3.43 0.016 0.018 0.022 0.41 0.46 0.56 0.058 0.060 0.064 1.47 1.52 1.63 0.008 0.010 0.014 0.20 0.25 0.36 0.360 0.380 9.14 9.65 0.290 0.300 0.310 7.37 7.62 7.87 0.245 0.
PAGE 55
W25Q80, W25Q16, W25Q32 12.
PAGE 56
W25Q80, W25Q16, W25Q32 12.4 8-contact 6x5 WSON Cont’d.
PAGE 57
W25Q80, W25Q16, W25Q32 12.5 16-Pin SOIC 300-mil (Winbond Package Code SF) SYMBOL MILLIMETERS INCHES MIN MAX MIN MAX A 2.36 2.64 0.093 0.104 A1 0.10 0.30 0.004 0.012 b 0.33 0.51 0.013 0.020 C 0.18 0.28 0.007 0.011 10.08 10.49 0.397 0.413 10.01 10.64 0.394 0.419 7.39 7.59 0.291 0.299 D (3) E E1 e (3) (2) 1.27 BSC 0.050 BSC L 0.39 1.27 0.015 0.050 θ 0 8 0 8o y --- o o 0.076 o --- 0.003 Notes: 1.
PAGE 58
W25Q80, W25Q16, W25Q32 ORDERING INFORMATION (1) 13. Notes: nd 1a. Only the 2 letter is used for the part marking. 1b. Standard bulk shipments are in Tube (shape E). Please specify alternate packing method, such as Tape and Reel (shape T), when placing orders. 1c. The “W” prefix is not included on the part marking.
PAGE 59
W25Q80, W25Q16, W25Q32 14. REVISION HISTORY VERSION DATE A 10/20/06 New Create Advanced A1 11/9/06 Various Figures 2, 3A-B, 13A–14C, 16, 24, 25 Table 10.2.2: Write Status Reg 1 and 2 Erase Suspend 10.2.21 tCHSH, tSHCH = 5nS A2 11/15/06 49 A3 2/22/07 20, 45, 49 & 57 Removed Burst Read Quad I/O Instruction. Updated ordering Information. Added transient voltage specification. A4 4/20/07 19, 28, 30 & 45 Added Mode Bit Reset instruction and description.
PAGE 60
W25Q80, W25Q16, W25Q32 Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life.