Preliminary W24L257
Publication Release Date: May 2000
- 5 - Revision A1
TIMING WAVEFORMS
Read Cycle 1
(Address Controlled)
Address
T
RC
T
AA
TOH
T
OH
DOUT
Read Cycle 2
(Chip Select Controlled)
CS1
D
OUT
T
CLZ
T
ACS
CHZ
T
Read Cycle 3
(Output Enable Controlled)
Address
T
RC
CS
T
AA
OE
T
AOE
T
OLZ
T
OH
T
ACS
D
OUT
CLZ
T
CHZ
T
T
OHZ
