Preliminary W24256
Publication Release Date: October 1999
- 5 - Revision A1
TIMING WAVEFORMS
Read Cycle 1
(Address Controlled)
Address
T
RC
T
AA
T
OH
TOH
D
OUT
Read Cycle 2
(Chip Select Controlled)
CS
D
OUT
TCLZ
TACS
CHZ
T
Read Cycle 3
(Output Enable Controlled)
Address
T
RC
CS
D
OUT
T
AA
OE
T
AOE
TOLZ
T
OH
CLZ
T
CHZ
T
T
ACS
T
OHZ
