Features • • • • • • • 6.5 µm x 6.5 µm Photodiode Pixel, at 6.5 µm Pitch 2 x 2 Outputs High Output Data Rate: 4 x 5 MHz High Dynamic Range: 10000: 1 Antiblooming and Exposure Time Control Very Low Lag 56 lead 0.6" DIL Package Description Atmel’s TH7834C is a linear sensor based on charge-coupled device (CCD) technology.
Pin Description Pin Number Symbol Designation 1 VOS1 Output 1 (Odd Pixels) 2 VDR1 Reset DC Bias (Output 1) 3 VS1 Amplifier Source Bias (Output 1) 4 ΦR1-2 Reset Clock (Outputs 1 and 2) 5, 9, 14, 15, 20, 24, 33, 37, 42, 43, 48, 52 VSS Substrate Bias (Ground) 6, 34 VST Pixel Storage Gate DC Bias 7 ΦA1-2 Antiblooming and/or Exposure Time Control 8 VGS1-2 Output Gate DC Bias 10 Φ3A Register Main Transport Clock 11 Φ1A Register Main Transport Clock 12 Φ4A Register Main Transport
TH7834C Pin Description (Continued) Pin Number Symbol Designation 46 Φ1B Register Main Transport Clock 47 Φ3B Register Main Transport Clock 49 ΦP1-2 Transfer Clock 50 VA1-2 Antiblooming Diode Bias 51 ΦLS1-2 Register End Transport Clock 53 VDD1-2 Amplifier Drain Supplies (Outputs 1, 2) 54 VS2 Amplifier Source Bias (Output 2) 55 VDR2 Reset DC Bias (Output 2) 56 Notes: VOS2 Output 2 (Even Pixels) 1.
The four CCD shift registers have separated clocks. The output signal can be, then, delivered simultaneously or sequentially on the four outputs. The four CCD shift registers are designed with 4 separated gates. According to the gate connection, the signal can be read through 2 or 4 output amplifiers. According to gate connection, 2 or 4 output operating mode can be chosen.
TH7834C Readout Shift Register Clocking All gates of the 4 CCD shift registers are separated, enabling two or four output readout modes.
Operating Precautions Shorting the video outputs to VSS or VDD, even temporarily, can permanently damage the output amplifiers. Operating Conditions (T = 25°C) Table 1. DC Characteristics Value Parameter Symbol Min. Typ. Max. Unit VDD1-2, VDD3-4 14.5 15 15.5 V VSS 0 0 V VDR1, VDR2, VDR3, VDR4 VDD - 0.5 V VS1, VS2, VS3, VS4 0 V Output Amplifier Drain Supply Substrate Voltage Reset DC Bias Output Amplifier Source Bias Output Gate DC Bias VGS1-2, VGS3-4 2.2 2.4 2.6 V VST 3.
TH7834C • Each video line in four output operating mode consists in: – 30 inactive pre-scan, (not connected to pixels), – 6 dark references, – 4 isolation elements, (inactive, not connected to pixels), – 3 non-useful pixels, – 3 000 useful pixels of the line. N = number of pixel periods (Tp) during readout period (see Figure 5). Four output operating mode: N ≥ 3043. Two output operating mode: N ≥ 6086. (ΦLS can be clocked during the line blancking). Figure 4.
Cross over of complementary clocks (ΦL1 and ΦL2) preferably at 50% of their amplitude. Note: Generally, the difference between the floating diode level and signal level is the sum of several signals: • Register clock feedthrough • Average CCD register dark signal proportional to CCD clock period, mode, temperature • Pixel dark signal (depending upon temperature and exposure time) • Pixel signal under illumination Table 2.
TH7834C Table 4. Drive Clock Capacitances Operating Frequencies(1) Symbol Function/Clock Capacitive Network ΦL1 ΦL1, ΦL2 Register Main Transport Clock ΦLS1-2, ΦLS3-4 Register End Transfer Clock ΦP1-2, ΦP3-4 160pF ΦL2 250pF 320pF Total Max. Frequency ΦL1: 570 pF ΦL2: 640 pF for one CCD(1) 10 MHz ≤ 50 pF per phase 10 MHz 80 pF per phase Pulse duration ≥ 2 µs Period: ≥ 608.
Electro-optical Performance • General measurement conditions: Tc = 25°C; Ti = 1 ms; FΦLA, FΦLB, FΦLC, FΦLD = 5 MHz, readout through 4 outputs. • Light source: tungsten filament lamp (2,854 K) + BG 38 filter (2 mm thick) + F/3.5 aperture. The BG 38 filter limits the spectrum to 700 nm. In these conditions, 1 µJ/cm2 corresponds to 3.5 lux.s. • Typical operating conditions (see Table 1, 2, 3 and 4).
TH7834C Figure 6. Typical Spectral Responsitivity 8.0 η=0.8 η=0.7 7.2 η=0.6 6.4 (V/µJ/cm 2) 5.6 4.8 4.0 3.2 2.4 1.6 0.8 0 400 500 600 700 800 900 1000 1100 Lambda (nm) Figure 7. VSAT versus ΦA Low Level Typical Curve Vsat. (mV) Antiblooming OFF Antiblooming ON 3600 3400 3200 3000 2800 2600 2400 2200 2000 1800 1600 1400 1200 1000 800 600 400 200 0 VST = 4 V Φ R Low level = 1.5V VA = 13V 0 1 2 3 4 5 6 7 8 8.
Table 7. Exposure Time Reduction Conditions Value Parameter Symbol Min. Typ. Max. Unit Antiblooming Diode Bias VA1-2. VA3-4 14 15.5 15 V Antiblooming And Expose Time Control Period 1 ΦA1-2, ΦA3-4 Period 2 to be adjusted 9.5 V 10 10.5 V Figure 8.
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