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Features

• Pixel Size: 13 µm x 13 µm (13 µm pitch)

• High Data Output Rate: 20 MHz typ

• High Responsivity and Resolution over a Wide Spectral Range: from Blue (400 nm) up

to Near Infrared (1100 nm)

• Improved Dark Signal and Photo Response Uniformity

• Low Temporal Noise and High Dynamic Range: Over 6000/1

• Ease and Flexibility of Operation:

– Only two External Basic Drive Clocks

– Internal or External Sample and Reset Clocks

• 24-lead DIL Package

Pin Identification

Pin Number Symbol Designation

OSA

Video Output Signal A (Odd Channel)

2 Φ

ECHA

A Channel Sample-and-hold Gate Input

3SΦ

ECHA

A Channel Internal Sample Clock-output

4 Φ

A Channel External Reset Clock Input

Output Amplifier Drain And Internal Logic Supply

9TP3TestPoint3

10 TP2 Test Point 2

11 VT Register And Photosensitive Zone DC Bias

12 TP1 Test Point 1

13 V

Substrate Bias (Ground)

15 Φ

Transfer Clock

16 Φ

17 V

Output Gate DC Bias

18 Φ

B Channel External Reset Clock Input

19 V

INH

Internal Sample Clock Inhibition

21 SΦ

ECHB

B Channel Internal Sample Clock Input

22 Φ

ECHB

B Channel Sample-and-hold Gate Input

23 V

OSB

Video Output Signal B (Even Channel)

24 V

Reset DC Bias

5, 6, 7, 14, 20 DNC Do Not Connected

OSA

ECHA

DNC

TP3

TP2

TP1

OSB

ECHB

DNC

INH

DNC

TH7804A

Linear Charged

Couple Device

(CCD) Image

Sensor 1024

Pixels

TH7804A

Rev. 1989A–IMAGE–05/02

Summary of content (11 pages)

PAGE 1
Features • Pixel Size: 13 µm x 13 µm (13 µm pitch) • High Data Output Rate: 20 MHz typ • High Responsivity and Resolution over a Wide Spectral Range: from Blue (400 nm) up to Near Infrared (1100 nm) • Improved Dark Signal and Photo Response Uniformity • Low Temporal Noise and High Dynamic Range: Over 6000/1 • Ease and Flexibility of Operation: – Only two External Basic Drive Clocks – Internal or External Sample and Reset Clocks • 24-lead DIL Package Pin Identification Pin Number Symbol Designation 1 V
PAGE 2
Absolute Maximum Ratings* Storage Temperature ..................................... -55°C to +150°C Operating Temperature....................................... 0°C to +70°C Thermal Cycling..........................................................15°C/mn *NOTICE: Stresses above those listed under absolute maximum ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
PAGE 3
TH7804A Operating Conditions (T = 25°) Table 1. DC Bias Characteristics Value Parameter Symbol Min. Typ. Max Unit Output Amplifier Drain Supply VDD 14 15 16 V Reset DC Bias VDR VDD - 2.4 VDD - 2 VDD - 1 V Output Gate DC Bias VGS 5.5 6 6.5 V Photosensitive Zone And Register DC Bias VT 0.95 VTN VTN 1.05 V TN V Substrate Bias VSS 0.0 0.0 V Test Point 1 TP1 VDD V (2) TP2, TP3 VSS V (2) Tests Points 2 And 3 Notes: Remark (1) 1. Nominal value of VT: VTN = 6.
PAGE 4
Figure 1. Basic Test Configuration Figure 2.
PAGE 5
TH7804A Table 3. Drive Clock Characteristics (see Figure 2) Value Parameter Transfer Clock Register Transport Clock Symbol ΦP, ΦT Logic Min. Typ. Max. High 11 13 14 Low 0.0 0.4 0.6 Unit Remark V (1) Register Transport Clock Capacitance CΦT 400 700 pF Transfer Clock Capacitance CΦP 130 200 pF Note: 1. Transients under 0.0V in the clock pulses will lead to charge injection, causing a localized increase in the dark signal.
PAGE 6
Table 5. Electro-optical Performance Value Parameter Symbol Min. Typ. Max. Unit Remark Saturation Output Voltage VSAT 1.3 1.8 2.3 V (1) (2) Saturation Exposure ESAT Responsivity R 4.5 0.30 µJ/cm2 6 V/µJ/cm2 Responsivity Unbalance ∆R/R 2 8 % (3) Photo Response Non-uniformity Peak-to-peak PRNU ±3 ±10 % VOS VOS = 50 mV to 1V Contrast Transfer Function at FN (38 I p/mm) CTF 70 % VOS = 0.
PAGE 7
TH7804A Figure 4. CTF Typical Curves (2854 K Source) Electro-optical Performance Without Infrared Cut-off Filtering The TH7804A’s special semiconductor process enables it to exploit the silicon's high near infrared sensitivity while maintaining good imaging performance in terms of response uniformity and resolution. Typical changes in performance with and without IR filtering are summarized below.
PAGE 8
Table 6. Selection of Operating Modes Option Implementation No Sampling ΦECHA (2) and ΦECHB (22) connected to VDD SΦECHA (3) and SΦECHB (21) unconnected VINH (19) connected to VDD Sampling by External Clocks Sampling clocks connected to ΦECHA ΦECHB SΦECHA and SΦECHB unconnected VINH (19) connected to VDD Reset Control by External Clocks Note: Remarks (1) see Figure 5 for sampling clock timing (1) Ext. ΦRA on ΦRA (4) input Ext. ΦRB on ΦRB (18) see Figure 4 for reset clock timing 1.
PAGE 9
TH7804A Figure 5. Timing Diagram — Clocks and Video Output Timing Diagram With and Without On-chip Sampling. External reset clocks improve electro-optical performance, as listed below. Other operating conditions and other electrooptical parameters remain unchanged. Table 8. Performance Improvements with External ΦRA and ΦRB Configuration Value Parameter Saturation Output Voltage Responsivity Dynamic Range Symbol Typ. Unit VSAT 2.
PAGE 10
Outline Drawing Z = 1.28 ± 0.23 2.16 Notes: 1. If an optical reference is needed, it is recommended to use the window face plane. 2. Variation of Z (azimuth) on the photosensitive area of a device is ≤ ±0.1 mm. 3. Value and tolerance of Y are applicable to each individual pixel of the photosensitive line.
PAGE 11
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