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Rev. C – 3-Dec-01

Features

• 80C52 Compatible

– 8051 pin and instruction compatible

– Four 8-bit I/O ports + 2 I/O I2C Interface pins

– Three 16-bit timer/counters

– 256 bytes scratch pad RAM

– 10 Interrupt sources with 4 priority levels

– Dual Data Pointer

• Variable length MOVX for slow RAM/peripherals

• ISP (In System Programming) using standard V

power supply.

• Boot ROM contains low level FLASH programming routines and a default serial loader

• High-Speed Architecture

– 40 MHz in standard mode

– 20 MHz in X2 mode (6 clocks/machine cycle)

• 32-Kbytes on-chip FLASH program / data Memory

– Byte and page (128 bytes) erase and write

– 10k write cycles

– On-chip 1024 bytes expanded RAM (XRAM)

– Software selectable size (0, 256, 512, 768, 1024 bytes)

– 256 bytes selected at reset for T87C51RB2/RC2 compatibility

• Keyboard interrupt interface on port P1

• 400-Kbits/s Multimaster I

C Interface

• SPI Interface (Master / Slave Mode)

• Sub clock 32kHz crystal oscillator

• 8-bit clock prescaler

• Improved X2 mode with independant selection for CPU and each peripheral

• Programmable Counter Array 5 Channels with:

– High Speed Output,

– Compare / Capture,

– Pulse Width Modulator,

– Watchdog Timer Capabilities

• Asynchronous port reset

• Full duplex Enhanced UART

• Dedicated Baud Rate Generator for UART

• Low EMI (inhibit ALE)

• Hardware Watchdog Timer (One-time enabled with Reset-Out)

• Power control modes:

– Idle Mode.

– Power-down mode.

– Power-Off Flag.

• Power supply: 4.5V to 5.5V or 2.7V to 3.6V

• Temperature ranges: Commercial (0 to +70°C) and industrial (-40°Cto+85°C).

• Packages: PLC44, VQFP44

Description

T89C51IC2 is a high performance FLASH version of the 80C51 8-bit microcontrollers.

It contains a 32-Kbytes Flash memory block for program and data.

The 32-Kbytes FLASH memory can be programmed either in parallel mode or in serial

mode with the ISP capability or with software. The programming voltage is internally

generated from the standard V

pin.

The T89C51IC2 retains all features of the 80C52 with 256 bytes of internal RAM, a 7-

source 4-level interrupt controller and three timer/counters.

8-bit

Microcontroller

with Flash and

C Interface

T89C51IC2

Summary

Summary of content (10 pages)

PAGE 1
Features • 80C52 Compatible • • • • • • • • • • • • • • • • • • • • • – 8051 pin and instruction compatible – Four 8-bit I/O ports + 2 I/O I2C Interface pins – Three 16-bit timer/counters – 256 bytes scratch pad RAM – 10 Interrupt sources with 4 priority levels – Dual Data Pointer Variable length MOVX for slow RAM/peripherals ISP (In System Programming) using standard VCC power supply.
PAGE 2
In addition, the T89C51IC2 has a 32kHz Subsidiary clock Oscillator, a Programmable Counter Array, an XRAM of 1024 byte, a Hardware Watchdog Timer, a Keyboard Interface, a I2C Interface, a SPI Interface, a more versatile serial channel that facilitates multiprocessor communication (EUART) and a speed improvement mechanism (X2 mode). The fully static design of the T89C51IC2 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data.
PAGE 3
T89C51IC2 SFR Mapping The Special Function Registers (SFRs) of the T89C51IC2 fall into the following categories: • C51 core registers: ACC, B, DPH, DPL, PSW, SP • I/O port registers: P0, P1, P2, P3, PI2 • Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H • Serial I/O port registers: SADDR, SADEN, SBUF, SCON • PCA (Programmable Counter Array) registers: CCON, CCAPMx, CL, CH, CCAPxH, CCAPxL (x: 0 to 4) • Power and clock control registers: PCON • Hardware Watc
PAGE 4
Table 2. SFR mapping Table below shows all SFRs with their address and their reset value.
PAGE 5
T89C51IC2 P0.2/AD2 P0.3/AD3 P0.1/AD1 P0.0/AD0 VCC XTALB2 P1.0/T2/XTALB1 P1.1/T2EX/SS P1.2/ECI P1.3/CEX0 P1.4/CEX1 Pin Configurations 6 5 4 3 2 1 44 43 42 41 40 P1.5/CEX2/MISO 39 38 P0.4/AD4 P1.6/CEX3/SCK 7 8 P1.7/CEx4/MOSI 9 37 P0.6/AD6 RST 10 36 P0.7/AD7 P3.0/RxD 35 34 EA PI2.1/SDA 11 12 P3.1/TxD 13 33 ALE/PROG P3.2/INT0 P3.3/INT1 14 15 32 31 PSEN P3.4/T0 P3.5/T1 16 30 P2.6/A14 17 29 P2.5/A13 PLCC44 P0.5/AD5 PI2.0/SCL P2.7/A15 P0.3/AD3 P0.2/AD2 P2.
PAGE 6
Table 1. Pin Description for 40/44 pin packages Pin Number Type Mnemonic PLCC44 VQFP44 1.4 Name and Function VSS 22 16 I Ground: 0V reference VCC 44 38 I Power Supply: This is the power supply voltage for normal, idle and power-down operation P0.0-P0.7 43-36 37-30 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high impedance inputs.
PAGE 7
T89C51IC2 Pin Number Type Mnemonic PLCC44 VQFP44 1.4 Name and Function I/O CEX4: Capture/Compare External I/O for PCA module 4 I/O MOSI: SPI Master Output Slave Input line When SPI is in master mode, MOSI outputs data to the slave peripheral. When SPI is in slave mode, MOSI receives data from the master controller. XTALA1 21 15 I Crystal A 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits.
PAGE 8
Pin Number Type Mnemonic PLCC44 VQFP44 1.4 RST 10 4 I/O ALE/PROG 33 27 O (I) PSEN 32 26 O Program Strobe ENable: The read strobe to external program memory. When executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory.
PAGE 9
T89C51IC2 Ordering Information Table 2.
PAGE 10
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