Owner's manual
Table Of Contents
- 8-bit MCU with CAN controller and Flash
- 1. Description
- 2. Features
- 3. Block Diagram
- 4. Pin Configuration
- 5. SFR Mapping
- 6. Clock
- 7. Program/Code Memory
- 8. Data Memory
- 9. EEPROM data memory
- 10. In-System-Programming (ISP)
- 11. Serial I/O Port
- 12. Timers/Counters
- 13. Timer 2
- 14. WatchDog Timer
- 15. Atmel CAN Controller
- 15.1. Introduction
- 15.2. CAN Controller Description
- 15.3. CAN Controller Mailbox and Registers Organization
- 15.4. IT CAN management
- 15.5. Bit Timing and BaudRate
- 15.6. Fault Confinement
- 15.7. Acceptance filter
- 15.8. Data and Remote frame
- 15.9. Time Trigger Communication (TTC) and Message Stamping
- 15.10. CAN Autobaud and Listening mode
- 15.11. CAN SFR’s
- 15.12. Registers
- 16. Programmable Counter Array PCA
- 17. Analog-to-Digital Converter (ADC)
- 18. Interrupt System
- 19. Electrical Characteristics
- 20. Ordering Information
Rev.A - May 17, 2001 99
Preliminary
T89C51CC02
CANTCON (S:A1h)
CAN Timer ClockControl
Reset Value: 00h
Figure 97. CANTCON Register
CANTIMH (S:ADh Read Only)
CAN Timer High
Reset Value: 0000 0000b
Figure 98. CANTIMH Register
CANTIML (S:ACh Read Only)
CAN Timer Low
Reset Value: 0000 0000b
Figure 99. CANTIML Register
7 6 5 4 3 2 1 0
TPRESC 7 TPRESC 6 TPRESC 5 TPRESC 4 TPRESC 3 TPRESC 2 TPRESC 1 TPRESC 0
Bit Number Bit Mnemonic Description
7-0 TPRESC7:0
Timer Prescaler of CAN Timer
This register is a prescaler for the main timer upper counter
range=0to255.
See Figure 63.
7 6 5 4 3 2 1 0
CANGTIM 15 CANGTIM 14 CANGTIM 13 CANGTIM 12 CANGTIM 11 CANGTIM 10 CANGTIM 9 CANGTIM 8
Bit Number Bit Mnemonic Description
7-0 CANGTIM15:8
High byte of Message Timer
See Figure 63.
7 6 5 4 3 2 1 0
CANGTIM 7 CANGTIM 6 CANGTIM 5 CANGTIM 4 CANGTIM 3 CANGTIM 2 CANGTIM 1 CANGTIM 0
Bit Number Bit Mnemonic Description
7-0 CANGTIM7:0
Low byte of Message Timer
See Figure 63.