Owner's manual
Table Of Contents
- 8-bit MCU with CAN controller and Flash
- 1. Description
- 2. Features
- 3. Block Diagram
- 4. Pin Configuration
- 5. SFR Mapping
- 6. Clock
- 7. Program/Code Memory
- 8. Data Memory
- 9. EEPROM data memory
- 10. In-System-Programming (ISP)
- 11. Serial I/O Port
- 12. Timers/Counters
- 13. Timer 2
- 14. WatchDog Timer
- 15. Atmel CAN Controller
- 15.1. Introduction
- 15.2. CAN Controller Description
- 15.3. CAN Controller Mailbox and Registers Organization
- 15.4. IT CAN management
- 15.5. Bit Timing and BaudRate
- 15.6. Fault Confinement
- 15.7. Acceptance filter
- 15.8. Data and Remote frame
- 15.9. Time Trigger Communication (TTC) and Message Stamping
- 15.10. CAN Autobaud and Listening mode
- 15.11. CAN SFR’s
- 15.12. Registers
- 16. Programmable Counter Array PCA
- 17. Analog-to-Digital Converter (ADC)
- 18. Interrupt System
- 19. Electrical Characteristics
- 20. Ordering Information
Rev.A - May 17, 2001 97
Preliminary
T89C51CC02
CANIDM2 for V2.0 part B (S:C5h)
CAN Identifier Mask Registers 2
NOTE:
The ID Mask is only used for reception.
No default value after reset.
Figure 93. CANIDM2 Register for V2.0 part B
CANIDM3 for V2.0 part B (S:C6h)
CAN Identifier Mask Registers 3
NOTE:
The ID Mask is only used for reception.
No default value after reset.
Figure 94. CANIDM3 Register for V2.0 part B
7 6 5 4 3 2 1 0
IDMSK 20 IDMSK 19 IDMSK 18 IDMSK 17 IDMSK 16 IDMSK 15 IDMSK 14 IDMSK 13
Bit Number Bit Mnemonic Description
7-0 IDMSK20:13
IDentifier mask value
0 - comparison true forced.
1 - bit comparison enabled.
See Figure 62.
7 6 5 4 3 2 1 0
IDMSK 12 IDMSK 11 IDMSK 10 IDMSK 9 IDMSK 8 IDMSK 7 IDMSK 6 IDMSK 5
Bit Number Bit Mnemonic Description
7-0 IDMSK12:5
IDentifier mask value
0 - comparison true forced.
1 - bit comparison enabled.
See Figure 62.