Owner's manual
Table Of Contents
- 8-bit MCU with CAN controller and Flash
- 1. Description
- 2. Features
- 3. Block Diagram
- 4. Pin Configuration
- 5. SFR Mapping
- 6. Clock
- 7. Program/Code Memory
- 8. Data Memory
- 9. EEPROM data memory
- 10. In-System-Programming (ISP)
- 11. Serial I/O Port
- 12. Timers/Counters
- 13. Timer 2
- 14. WatchDog Timer
- 15. Atmel CAN Controller
- 15.1. Introduction
- 15.2. CAN Controller Description
- 15.3. CAN Controller Mailbox and Registers Organization
- 15.4. IT CAN management
- 15.5. Bit Timing and BaudRate
- 15.6. Fault Confinement
- 15.7. Acceptance filter
- 15.8. Data and Remote frame
- 15.9. Time Trigger Communication (TTC) and Message Stamping
- 15.10. CAN Autobaud and Listening mode
- 15.11. CAN SFR’s
- 15.12. Registers
- 16. Programmable Counter Array PCA
- 17. Analog-to-Digital Converter (ADC)
- 18. Interrupt System
- 19. Electrical Characteristics
- 20. Ordering Information
96 Rev.A - May 17, 2001
Preliminary
T89C51CC02
CANIDM4 for V2.0 part A (S:C7h)
CAN Identifier Mask Registers 4
NOTE:
The ID Mask is only used for reception.
No default value after reset.
Figure 91. CANIDM4 Register for V2.0 part A
CANIDM1 for V2.0 part B (S:C4h)
CAN Identifier Mask Registers 1
NOTE:
The ID Mask is only used for reception.
No default value after reset.
Figure 92. CANIDM1 Register for V2.0 part B
7 6 5 4 3 2 1 0
-----RTRMSK - IDEMSK
Bit Number Bit Mnemonic Description
7-3 -
Reserved
The values read from these bits are indeterminate. Do not set these bits.
2 RTRMSK
Remote transmission request mask value
0 - comparison true forced.
1 - bit comparison enabled.
1-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
0 IDEMSK
IDentifier Extension mask value
0 - comparison true forced.
1 - bit comparison enabled.
7 6 5 4 3 2 1 0
IDMSK 28 IDMSK 27 IDMSK 26 IDMSK 25 IDMSK 24 IDMSK 23 IDMSK 22 IDMSK 21
Bit Number Bit Mnemonic Description
7-0 IDMSK28:21
IDentifier mask value
0 - comparison true forced.
1 - bit comparison enabled.
See Figure 62.