Owner's manual
Table Of Contents
- 8-bit MCU with CAN controller and Flash
- 1. Description
- 2. Features
- 3. Block Diagram
- 4. Pin Configuration
- 5. SFR Mapping
- 6. Clock
- 7. Program/Code Memory
- 8. Data Memory
- 9. EEPROM data memory
- 10. In-System-Programming (ISP)
- 11. Serial I/O Port
- 12. Timers/Counters
- 13. Timer 2
- 14. WatchDog Timer
- 15. Atmel CAN Controller
- 15.1. Introduction
- 15.2. CAN Controller Description
- 15.3. CAN Controller Mailbox and Registers Organization
- 15.4. IT CAN management
- 15.5. Bit Timing and BaudRate
- 15.6. Fault Confinement
- 15.7. Acceptance filter
- 15.8. Data and Remote frame
- 15.9. Time Trigger Communication (TTC) and Message Stamping
- 15.10. CAN Autobaud and Listening mode
- 15.11. CAN SFR’s
- 15.12. Registers
- 16. Programmable Counter Array PCA
- 17. Analog-to-Digital Converter (ADC)
- 18. Interrupt System
- 19. Electrical Characteristics
- 20. Ordering Information
92 Rev.A - May 17, 2001
Preliminary
T89C51CC02
CANIDT1 for V2.0 part A (S:BCh)
CAN Identifier Tag Registers 1
No default value after reset.
Figure 80. CANIDT1 Register for V2.0 part A
CANIDT2 for V2.0 part A (S:BDh)
CAN Identifier Tag Registers 2
No default value after reset.
Figure 81. CANIDT2 Register for V2.0 part A
CANIDT3 for V2.0 part A (S:BEh)
CAN Identifier Tag Registers 3
No default value after reset.
Figure 82. CANIDT3 Register for V2.0 part A
7 6 5 4 3 2 1 0
IDT 10 IDT 9 IDT 8 IDT 7 IDT 6 IDT 5 IDT 4 IDT 3
Bit Number Bit Mnemonic Description
7-0 IDT10:3
IDentifier tag value
See Figure 62.
7 6 5 4 3 2 1 0
IDT 2 IDT 1 IDT 0 - - - - -
Bit Number Bit Mnemonic Description
7-5 IDT2:0
IDentifier tag value
See Figure 62.
4-0 -
Reserved
The values read from these bits are indeterminate. Do not set these bits.
7 6 5 4 3 2 1 0
--------
Bit Number Bit Mnemonic Description
7-0 -
Reserved
The values read from these bits are indeterminate. Do not set these bits.