Owner's manual
Table Of Contents
- 8-bit MCU with CAN controller and Flash
- 1. Description
- 2. Features
- 3. Block Diagram
- 4. Pin Configuration
- 5. SFR Mapping
- 6. Clock
- 7. Program/Code Memory
- 8. Data Memory
- 9. EEPROM data memory
- 10. In-System-Programming (ISP)
- 11. Serial I/O Port
- 12. Timers/Counters
- 13. Timer 2
- 14. WatchDog Timer
- 15. Atmel CAN Controller
- 15.1. Introduction
- 15.2. CAN Controller Description
- 15.3. CAN Controller Mailbox and Registers Organization
- 15.4. IT CAN management
- 15.5. Bit Timing and BaudRate
- 15.6. Fault Confinement
- 15.7. Acceptance filter
- 15.8. Data and Remote frame
- 15.9. Time Trigger Communication (TTC) and Message Stamping
- 15.10. CAN Autobaud and Listening mode
- 15.11. CAN SFR’s
- 15.12. Registers
- 16. Programmable Counter Array PCA
- 17. Analog-to-Digital Converter (ADC)
- 18. Interrupt System
- 19. Electrical Characteristics
- 20. Ordering Information
90 Rev.A - May 17, 2001
Preliminary
T89C51CC02
CANCONCH (S:B3h)
CAN message object Control and DLC Register
No default value after reset
Figure 78. CANCONCH Register
7 6 5 4 3 2 1 0
CONCH 1 CONCH 0 RPLV IDE DLC 3 DLC 2 DLC 1 DLC 0
Bit Number Bit Mnemonic Description
7-6 CONCH1:0
Configuration of message object
CONCH1 CONCH0
0 0: disable
0 1: Transmitter
1 0: Receiver
1 1: Receiver Buffer
NOTE:
The user must re-write the configuration to enable the corresponding bit in the CANEN1:2 registers.
5 RPLV
Reply valid
Used in the automatic reply mode after receiving a remote frame
0 - reply not ready.
1 - reply ready & valid.
4 IDE
Identifier extension
0 - CAN standard rev 2.0 A (ident = 11 bits).
1 - CAN standard rev 2.0 B (ident = 29 bits).
3-0 DLC3:0
Data length code
Number of bytes in the data field of the message.
The range of DLC is from 0 up to 8.
This value is updated when a frame is received (data or remote frame).
If the expected DLC differs from the incoming DLC, a warning appears in the CANSTCH register.
See Figure 62.