Owner's manual
Table Of Contents
- 8-bit MCU with CAN controller and Flash
- 1. Description
- 2. Features
- 3. Block Diagram
- 4. Pin Configuration
- 5. SFR Mapping
- 6. Clock
- 7. Program/Code Memory
- 8. Data Memory
- 9. EEPROM data memory
- 10. In-System-Programming (ISP)
- 11. Serial I/O Port
- 12. Timers/Counters
- 13. Timer 2
- 14. WatchDog Timer
- 15. Atmel CAN Controller
- 15.1. Introduction
- 15.2. CAN Controller Description
- 15.3. CAN Controller Mailbox and Registers Organization
- 15.4. IT CAN management
- 15.5. Bit Timing and BaudRate
- 15.6. Fault Confinement
- 15.7. Acceptance filter
- 15.8. Data and Remote frame
- 15.9. Time Trigger Communication (TTC) and Message Stamping
- 15.10. CAN Autobaud and Listening mode
- 15.11. CAN SFR’s
- 15.12. Registers
- 16. Programmable Counter Array PCA
- 17. Analog-to-Digital Converter (ADC)
- 18. Interrupt System
- 19. Electrical Characteristics
- 20. Ordering Information
88 Rev.A - May 17, 2001
Preliminary
T89C51CC02
CANBT2 (S:B5h)
CAN Bit Timing Registers 2
Note:
The CAN controller bit timing registers must be accessed only if the CAN controller is disabled with the ENA bit of the CANGCON register set to 0.
See Figure 60.
No default value after reset.
Figure 75. CANBT2 Register
7 6 5 4 3 2 1 0
- SJW 1 SJW 0 - PRS 2 PRS 1 PRS 0 -
Bit Number Bit Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6-5 SJW1:0
Re-synchronization jump width
To compensate for phase shifts between clock oscillators of different bus controllers, the controller
must re-synchronize on any relevant signal edge of the current transmission.
The synchronization jump width defines the maximum number of clock cycles. A bit period may be
shortened or lengthened by a re-synchronization.
4-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3-1 PRS2:0
Programming time segment
This part of the bit time is used to compensate for the physical delay times within the network. It is
twice the sum of the signal propagation time on the bus line, the input comparator delay and the
output driver delay.
0-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Tsjw Tscl SJW 10,][ 1+()×=
Tprs Tscl PRS 2…0][ 1+()×=