Owner's manual
Table Of Contents
- 8-bit MCU with CAN controller and Flash
- 1. Description
- 2. Features
- 3. Block Diagram
- 4. Pin Configuration
- 5. SFR Mapping
- 6. Clock
- 7. Program/Code Memory
- 8. Data Memory
- 9. EEPROM data memory
- 10. In-System-Programming (ISP)
- 11. Serial I/O Port
- 12. Timers/Counters
- 13. Timer 2
- 14. WatchDog Timer
- 15. Atmel CAN Controller
- 15.1. Introduction
- 15.2. CAN Controller Description
- 15.3. CAN Controller Mailbox and Registers Organization
- 15.4. IT CAN management
- 15.5. Bit Timing and BaudRate
- 15.6. Fault Confinement
- 15.7. Acceptance filter
- 15.8. Data and Remote frame
- 15.9. Time Trigger Communication (TTC) and Message Stamping
- 15.10. CAN Autobaud and Listening mode
- 15.11. CAN SFR’s
- 15.12. Registers
- 16. Programmable Counter Array PCA
- 17. Analog-to-Digital Converter (ADC)
- 18. Interrupt System
- 19. Electrical Characteristics
- 20. Ordering Information

78 Rev.A - May 17, 2001
Preliminary
T89C51CC02
15.9. Time Trigger Communication (TTC) and Message Stamping
The T89C51CC02 has a programmable 16-bit Timer (CANTIMH&CANTIML) for message stamp and TTC.
This CAN Timer starts after the CAN controller is enabled by the ENA bit in the CANGCON register.
Two user modes of the timer are implemented:
• Time Trigger Communication:
Catch of this timer in the CANTTCH & CANTTCL registers on SOF or EOF, depending on the SYNCTTC
bit in the CANGCON register, when the network is configured in TTC by the TTC bit in the CANGCON register.
In this mode, CAN only sends the frame once, even if an error occurs.
• Message Stamping
Catch of this timer in the CANSTMPH & CANSTMPL registers of the message object which received or sent
the frame.
All messages can be stamps.
The stamping of a received frame occurs when the RxOk flag is set.
The stamping of a sent frame occurs when the TxOk flag is set.
The CAN Timer works in a loopback mode (0x0000... 0xFFFF, 0x0000) which serves as a time base to stamp all
received or transmitted messages.
When the timer overflows from 0xFFFF to 0x0000, an interrupt is generated if the ETIM bit of the CAN Timer
in a micro-controller interrupt system register is set.
Figure 63. Block diagram of CAN Timer
EOF on CAN frame
ENA
CANGCON.1
CANTCON
RXOK i
CANSTCH.5
TXOK i
CANSTCH.4
÷ 6
Fcan
CLOCK
SOF on CAN frame
TTC
CANGCON.5
SYNCTTC
CANGCON.4
CANTTCH & CANTTCL
CANSTMPH & CANSTMPL
CANTIMH & CANTIML
OVRTIM
CANGIT.5
When 0xFFFF to 0x0000