Owner's manual
Table Of Contents
- 8-bit MCU with CAN controller and Flash
- 1. Description
- 2. Features
- 3. Block Diagram
- 4. Pin Configuration
- 5. SFR Mapping
- 6. Clock
- 7. Program/Code Memory
- 8. Data Memory
- 9. EEPROM data memory
- 10. In-System-Programming (ISP)
- 11. Serial I/O Port
- 12. Timers/Counters
- 13. Timer 2
- 14. WatchDog Timer
- 15. Atmel CAN Controller
- 15.1. Introduction
- 15.2. CAN Controller Description
- 15.3. CAN Controller Mailbox and Registers Organization
- 15.4. IT CAN management
- 15.5. Bit Timing and BaudRate
- 15.6. Fault Confinement
- 15.7. Acceptance filter
- 15.8. Data and Remote frame
- 15.9. Time Trigger Communication (TTC) and Message Stamping
- 15.10. CAN Autobaud and Listening mode
- 15.11. CAN SFR’s
- 15.12. Registers
- 16. Programmable Counter Array PCA
- 17. Analog-to-Digital Converter (ADC)
- 18. Interrupt System
- 19. Electrical Characteristics
- 20. Ordering Information
74 Rev.A - May 17, 2001
Preliminary
T89C51CC02
15.5. Bit Timing and BaudRate
The baud rate selection is made by Tbit calculation:
Tbit = Tsyns + Tprs + Tphs1 + Tphs2
1. Tsyns = Tscl = (BRP[5..0]+ 1) / Fcan.
2. Tprs = (1 to 8) * Tscl = (PRS[2..0]+ 1) * Tscl
3. Tphs1 = (1 to 8) * Tscl = (PHS1[2..0]+ 1) * Tscl
4. Tphs2 = (1 to 8) * Tscl = (PHS2[2..0]+ 1) * Tscl
5. Tsjw = (1 to 4) * Tscl = (SJW[1..0]+ 1) * Tscl
The total number of Tscl (Time Quanta) in a bit time is from 8 to 25.
Figure 60. General structure of a bit period
example:
For a Baud Rate of 100 kbit/s and Fosc = 12 MHz For have 10 TQ:
BRP=5
PRS=2
PHS2 = 2
PHS1 = 2
Bit Rate Prescaler
oscillator
1/ Fcan
Tscl
system clock
one nominal bit
Tsyns
(*)
Tprs
Sample Point
(*)
Synchronization Segment: SYNS
Tbit
Tsyns = 1xTscl (fixed)
data
Tbit Tsyns Tprs Tphs1 Tphs2++ +=
Tbit calculation:
Transmission Point
Tphs1 + Tsjw
(3)
Tphs2 - Tsjw
(4)
(1)
Phase error ≤ 0
(2)
Phase error ≥ 0
(3)
Phase error > 0
(4)
Phase error < 0
Tphs2
(2)
Tphs1
(1)