Owner's manual
Table Of Contents
- 8-bit MCU with CAN controller and Flash
- 1. Description
- 2. Features
- 3. Block Diagram
- 4. Pin Configuration
- 5. SFR Mapping
- 6. Clock
- 7. Program/Code Memory
- 8. Data Memory
- 9. EEPROM data memory
- 10. In-System-Programming (ISP)
- 11. Serial I/O Port
- 12. Timers/Counters
- 13. Timer 2
- 14. WatchDog Timer
- 15. Atmel CAN Controller
- 15.1. Introduction
- 15.2. CAN Controller Description
- 15.3. CAN Controller Mailbox and Registers Organization
- 15.4. IT CAN management
- 15.5. Bit Timing and BaudRate
- 15.6. Fault Confinement
- 15.7. Acceptance filter
- 15.8. Data and Remote frame
- 15.9. Time Trigger Communication (TTC) and Message Stamping
- 15.10. CAN Autobaud and Listening mode
- 15.11. CAN SFR’s
- 15.12. Registers
- 16. Programmable Counter Array PCA
- 17. Analog-to-Digital Converter (ADC)
- 18. Interrupt System
- 19. Electrical Characteristics
- 20. Ordering Information

Rev.A - May 17, 2001 73
Preliminary
T89C51CC02
To enable a transmission interrupt:
• Enable General CAN IT in the interrupt system register,
• Enable interrupt by message object, EICHi,
• Enable tranmission interrupt, ENTX.
To enable a reception interrupt:
• Enable General CAN IT in the interrupt system register,
• Enable interrupt by message object, EICHi,
• Enable reception interrupt, ENRX.
To enable an interrupt on message object error:
• Enable General CAN IT in the interrupt system register,
• Enable interrupt by message object, EICHi,
• Enable interrupt on error, ENERCH.
To enable an interrupt on general error:
• Enable General CAN IT in the interrupt system register,
• Enable interrupt on error, ENERG.
To enable an interrupt on Buffer-full condition:
• Enable General CAN IT in the interrupt system register,
• Enable interrupt on Buffer full, ENBUF.
To enable an interrupt when Timer overruns:
• Enable Overrun IT in the interrupt system register.
When an interrupt occurs, the corresponding message object bit is set in the SIT register.
To acknowledge an interrupt, the corresponding CANSTCH bits (RXOK, TXOK,...) or CANGIT bits (OVRTIM,
OVRBUF,...), must be cleared by the software application.
When the CAN node is in transmission and detects a Form Error in its frame, a bit Error will also be raised.
Consequently, two consecutive interrupts can occur, both due to the same error.
When a message object error occur and set in CANSTCH register, no general error are setting in CANGIE register.