Owner's manual
Table Of Contents
- 8-bit MCU with CAN controller and Flash
- 1. Description
- 2. Features
- 3. Block Diagram
- 4. Pin Configuration
- 5. SFR Mapping
- 6. Clock
- 7. Program/Code Memory
- 8. Data Memory
- 9. EEPROM data memory
- 10. In-System-Programming (ISP)
- 11. Serial I/O Port
- 12. Timers/Counters
- 13. Timer 2
- 14. WatchDog Timer
- 15. Atmel CAN Controller
- 15.1. Introduction
- 15.2. CAN Controller Description
- 15.3. CAN Controller Mailbox and Registers Organization
- 15.4. IT CAN management
- 15.5. Bit Timing and BaudRate
- 15.6. Fault Confinement
- 15.7. Acceptance filter
- 15.8. Data and Remote frame
- 15.9. Time Trigger Communication (TTC) and Message Stamping
- 15.10. CAN Autobaud and Listening mode
- 15.11. CAN SFR’s
- 15.12. Registers
- 16. Programmable Counter Array PCA
- 17. Analog-to-Digital Converter (ADC)
- 18. Interrupt System
- 19. Electrical Characteristics
- 20. Ordering Information
58 Rev.A - May 17, 2001
Preliminary
T89C51CC02
13. Timer 2
13.1. Introduction
The T89C51CC02 timer 2 is compatible with timer 2 in the 80C52.
It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2 that are cascade-
connected. It is controlled by T2CON register (See Table 47) and T2MOD register (See Table 48). Timer 2 operation
is similar to Timer 0 and Timer 1. C/T2 selects F
OSC
/6 (timer operation) or external pin T2 (counter operation)
as timer register input. Setting TR2 allows TL2 to be incremented by the selected input.
Timer 2 includes the following enhancements:
• Auto-reload mode (up or down counter)
• Programmable clock-output
13.2. Auto-Reload Mode
The auto-reload mode configures timer 2 as a 16-bit timer or event counter with automatic reload. This feature is
controlled by the DCEN bit in T2MOD register (See Table 48). Setting the DCEN bit enables timer 2 to count up
or down as shown in Figure 45. In this mode the T2EX pin controls the counting direction.
When T2EX is high, timer 2 up-counts. Timer overflow occurs at FFFFh which sets the TF2 flag and generates
an interrupt request. The overflow also causes the 16-bit value in RCAP2H and RCAP2L registers to be loaded
into the timer registers TH2 and TL2.
When T2EX is low, timer 2 down-counts. Timer underflow occurs when the count in the timer registers TH2 and
TL2 equals the value stored in RCAP2H and RCAP2L registers. The underflow sets TF2 flag and reloads FFFFh
into the timer registers.
The EXF2 bit toggles when timer 2 overflow or underflow, depending on the direction of the count. EXF2 does
not generate an interrupt. This bit can be used to provide 17-bit resolution.