Owner's manual
Table Of Contents
- 8-bit MCU with CAN controller and Flash
- 1. Description
- 2. Features
- 3. Block Diagram
- 4. Pin Configuration
- 5. SFR Mapping
- 6. Clock
- 7. Program/Code Memory
- 8. Data Memory
- 9. EEPROM data memory
- 10. In-System-Programming (ISP)
- 11. Serial I/O Port
- 12. Timers/Counters
- 13. Timer 2
- 14. WatchDog Timer
- 15. Atmel CAN Controller
- 15.1. Introduction
- 15.2. CAN Controller Description
- 15.3. CAN Controller Mailbox and Registers Organization
- 15.4. IT CAN management
- 15.5. Bit Timing and BaudRate
- 15.6. Fault Confinement
- 15.7. Acceptance filter
- 15.8. Data and Remote frame
- 15.9. Time Trigger Communication (TTC) and Message Stamping
- 15.10. CAN Autobaud and Listening mode
- 15.11. CAN SFR’s
- 15.12. Registers
- 16. Programmable Counter Array PCA
- 17. Analog-to-Digital Converter (ADC)
- 18. Interrupt System
- 19. Electrical Characteristics
- 20. Ordering Information
50 Rev.A - May 17, 2001
Preliminary
T89C51CC02
PCON (S:87h)
Power Control Register
Reset Value = 00X1 0000b
Not bit addressable
Figure 33. PCON Register
7 6 5 4 3 2 1 0
SMOD1 SMOD0 - POF GF1 GF0 PD IDL
Bit Number Bit Mnemonic Description
7 SMOD1
Serial port Mode bit 1
Set to select double baud rate in mode 1, 2 or 3.
6 SMOD0
Serial port Mode bit 0
Clear to select SM0 bit in SCON register.
Set to select FE bit in SCON register.
5-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4 POF
Power-Off Flag
Clear to recognize next reset type.
Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software.
3 GF1
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
2 GF0
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
1PD
Power-Down mode bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
0 IDL
Idle mode bit
Clear by hardware when interrupt or reset occurs.
Set to enter idle mode.