Owner's manual
Table Of Contents
- 8-bit MCU with CAN controller and Flash
- 1. Description
- 2. Features
- 3. Block Diagram
- 4. Pin Configuration
- 5. SFR Mapping
- 6. Clock
- 7. Program/Code Memory
- 8. Data Memory
- 9. EEPROM data memory
- 10. In-System-Programming (ISP)
- 11. Serial I/O Port
- 12. Timers/Counters
- 13. Timer 2
- 14. WatchDog Timer
- 15. Atmel CAN Controller
- 15.1. Introduction
- 15.2. CAN Controller Description
- 15.3. CAN Controller Mailbox and Registers Organization
- 15.4. IT CAN management
- 15.5. Bit Timing and BaudRate
- 15.6. Fault Confinement
- 15.7. Acceptance filter
- 15.8. Data and Remote frame
- 15.9. Time Trigger Communication (TTC) and Message Stamping
- 15.10. CAN Autobaud and Listening mode
- 15.11. CAN SFR’s
- 15.12. Registers
- 16. Programmable Counter Array PCA
- 17. Analog-to-Digital Converter (ADC)
- 18. Interrupt System
- 19. Electrical Characteristics
- 20. Ordering Information
44 Rev.A - May 17, 2001
Preliminary
T89C51CC02
10.7. Hardware Byte
Default value after erasing chip: FFh
NOTE:
Only the 4 MSB bits can be access by software.
The 4 LSB bits can only be access by parallel mode.
Figure 24. Hardware byte
7 6 5 4 3 2 1 0
X2B BLJB - - - LB2 LB1 LB0
Bit Number Bit Mnemonic Description
7 X2B
X2 Bit
Set this bit to start in standard mode
Clear this bit to start in X2 mode.
6 BLJB
Boot Loader Jump Bitt
Clear (=1)this bit to start the user’s application on next RESET (@0000h) located in FM0,
Set (=0)this bit to start the boot loader(@F800h) located in FM1.
5-3 -
Reserved
The value read from these bits are indeterminate.
2-0 LB2:0 Lock Bits