Owner's manual
Table Of Contents
- 8-bit MCU with CAN controller and Flash
- 1. Description
- 2. Features
- 3. Block Diagram
- 4. Pin Configuration
- 5. SFR Mapping
- 6. Clock
- 7. Program/Code Memory
- 8. Data Memory
- 9. EEPROM data memory
- 10. In-System-Programming (ISP)
- 11. Serial I/O Port
- 12. Timers/Counters
- 13. Timer 2
- 14. WatchDog Timer
- 15. Atmel CAN Controller
- 15.1. Introduction
- 15.2. CAN Controller Description
- 15.3. CAN Controller Mailbox and Registers Organization
- 15.4. IT CAN management
- 15.5. Bit Timing and BaudRate
- 15.6. Fault Confinement
- 15.7. Acceptance filter
- 15.8. Data and Remote frame
- 15.9. Time Trigger Communication (TTC) and Message Stamping
- 15.10. CAN Autobaud and Listening mode
- 15.11. CAN SFR’s
- 15.12. Registers
- 16. Programmable Counter Array PCA
- 17. Analog-to-Digital Converter (ADC)
- 18. Interrupt System
- 19. Electrical Characteristics
- 20. Ordering Information
Rev.A - May 17, 2001 27
Preliminary
T89C51CC02
7.4. Registers
FCON (S:D1h)
FLASH Control Register
Reset Value= 0000 0000b
Figure 12. FCON Register
7 6 5 4 3 2 1 0
FPL3 FPL2 FPL1 FPL0 FPS FMOD1 FMOD0 FBUSY
Bit Number Bit Mnemonic Description
7-4 FPL3:0
Programming Launch Command Bits
Write 5Xh followed by AXh to launch the programming according to FMOD1:0. (see Table 14.)
3 FPS
FLASH Map Program Space
Set to map the column latch space in the data memory space.
Clear to re-map the data memory space.
2-1 FMOD1:0
FLASH Mode
See Table 13 or Table 14.
0 FBUSY
FLASH Busy
Set by hardware when programming is in progress.
Clear by hardware when programming is done.
Can not be cleared by software.