Owner's manual
Table Of Contents
- 8-bit MCU with CAN controller and Flash
- 1. Description
- 2. Features
- 3. Block Diagram
- 4. Pin Configuration
- 5. SFR Mapping
- 6. Clock
- 7. Program/Code Memory
- 8. Data Memory
- 9. EEPROM data memory
- 10. In-System-Programming (ISP)
- 11. Serial I/O Port
- 12. Timers/Counters
- 13. Timer 2
- 14. WatchDog Timer
- 15. Atmel CAN Controller
- 15.1. Introduction
- 15.2. CAN Controller Description
- 15.3. CAN Controller Mailbox and Registers Organization
- 15.4. IT CAN management
- 15.5. Bit Timing and BaudRate
- 15.6. Fault Confinement
- 15.7. Acceptance filter
- 15.8. Data and Remote frame
- 15.9. Time Trigger Communication (TTC) and Message Stamping
- 15.10. CAN Autobaud and Listening mode
- 15.11. CAN SFR’s
- 15.12. Registers
- 16. Programmable Counter Array PCA
- 17. Analog-to-Digital Converter (ADC)
- 18. Interrupt System
- 19. Electrical Characteristics
- 20. Ordering Information
Rev.A - May 17, 2001 21
Preliminary
T89C51CC02
The FLASH memory enters a busy state as soon as programming is launched. In this state, the memory is no
more available for fetching code. Thus to avoid any erratic execution during programming, the CPU enters Idle
mode. Exit is automatically performed at the end of programming.
Caution:
Interrupts that may occur during programming time must be disable to avoid any spurious exit of the idle mode.
7.3.3. Status of the flash memory
The bit FBUSY in FCON register is used to indicate the status of programming.
FBUSY is set when programming is in progress.
7.3.4. Selecting FM1/FM1
The bit ENBOOT in AUXR1 register is used to choose between FM0 and FM1 mapped up to F800h.