Owner's manual
Table Of Contents
- 8-bit MCU with CAN controller and Flash
- 1. Description
- 2. Features
- 3. Block Diagram
- 4. Pin Configuration
- 5. SFR Mapping
- 6. Clock
- 7. Program/Code Memory
- 8. Data Memory
- 9. EEPROM data memory
- 10. In-System-Programming (ISP)
- 11. Serial I/O Port
- 12. Timers/Counters
- 13. Timer 2
- 14. WatchDog Timer
- 15. Atmel CAN Controller
- 15.1. Introduction
- 15.2. CAN Controller Description
- 15.3. CAN Controller Mailbox and Registers Organization
- 15.4. IT CAN management
- 15.5. Bit Timing and BaudRate
- 15.6. Fault Confinement
- 15.7. Acceptance filter
- 15.8. Data and Remote frame
- 15.9. Time Trigger Communication (TTC) and Message Stamping
- 15.10. CAN Autobaud and Listening mode
- 15.11. CAN SFR’s
- 15.12. Registers
- 16. Programmable Counter Array PCA
- 17. Analog-to-Digital Converter (ADC)
- 18. Interrupt System
- 19. Electrical Characteristics
- 20. Ordering Information
128 Rev.A - May 17, 2001
Preliminary
T89C51CC02
IPH1 (S:F7h)
Interrupt high priority Register 1
Reset Value = XXXX X000b
Figure 132. IPH1 Register
7 6 5 4 3 2 1 0
- - - - POVRH PADCH PCANH
Bit Number Bit Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2 POVRH
Timer overrun Interrupt Priority level most significant bit
POVRH POVRLPriority level
0 0 Lowest
01
10
1 1 Highest
1 PADCH
ADC Interrupt Priority level most significant bit
PADCH PADCL Priority level
0 0 Lowest
01
10
1 1 Highest
0 PCANH
CAN Interrupt Priority level most significant bit
PCANH PCANLPriority level
0 0 Lowest
01
10
1 1 Highest