Owner's manual
Table Of Contents
- 8-bit MCU with CAN controller and Flash
- 1. Description
- 2. Features
- 3. Block Diagram
- 4. Pin Configuration
- 5. SFR Mapping
- 6. Clock
- 7. Program/Code Memory
- 8. Data Memory
- 9. EEPROM data memory
- 10. In-System-Programming (ISP)
- 11. Serial I/O Port
- 12. Timers/Counters
- 13. Timer 2
- 14. WatchDog Timer
- 15. Atmel CAN Controller
- 15.1. Introduction
- 15.2. CAN Controller Description
- 15.3. CAN Controller Mailbox and Registers Organization
- 15.4. IT CAN management
- 15.5. Bit Timing and BaudRate
- 15.6. Fault Confinement
- 15.7. Acceptance filter
- 15.8. Data and Remote frame
- 15.9. Time Trigger Communication (TTC) and Message Stamping
- 15.10. CAN Autobaud and Listening mode
- 15.11. CAN SFR’s
- 15.12. Registers
- 16. Programmable Counter Array PCA
- 17. Analog-to-Digital Converter (ADC)
- 18. Interrupt System
- 19. Electrical Characteristics
- 20. Ordering Information
122 Rev.A - May 17, 2001
Preliminary
T89C51CC02
Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt
Enable register. This register also contains a global disable bit which must be cleared to disable all the interrupts
at the same time.
Each interrupt source can also be individually programmed to one of four priority levels by setting or clearing a
bit in the Interrupt Priority registers. The Table below shows the bit values and priority levels associated with each
combination.
Table 23. Priority Level Bit Values
A low-priority interrupt can be interrupted by a high priority interrupt but not by another low-priority interrupt. A
high-priority interrupt cannot be interrupted by any other interrupt source.
If two interrupt requests of different priority levels are received simultaneously, the request of the higher priority
level is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling
sequence determines which request is serviced. Thus within each priority level there is a second priority structure
determined by the polling sequence, see Table 24.
Table 24. Interrupt priority Within level
IPH.x IPL.x Interrupt Level Priority
0 0 0 (Lowest)
011
102
1 1 3 (Highest)
Interrupt Name Interrupt Address Vector Priority Number
external interrupt (INT0) 0003h 1
Timer0 (TF0) 000Bh 2
external interrupt (INT1) 0013h 3
Timer1 (TF1) 001Bh 4
PCA (CF or CCFn) 0033h 5
UART (RI or TI) 0023h 6
Timer2 (TF2) 002Bh 7
CAN (Txok, Rxok, Err or OvrBuf) 003Bh 8
ADC (ADCI) 0043h 9
CAN Timer Overflow (OVRTIM) 004Bh 10