Owner's manual
Table Of Contents
- 8-bit MCU with CAN controller and Flash
- 1. Description
- 2. Features
- 3. Block Diagram
- 4. Pin Configuration
- 5. SFR Mapping
- 6. Clock
- 7. Program/Code Memory
- 8. Data Memory
- 9. EEPROM data memory
- 10. In-System-Programming (ISP)
- 11. Serial I/O Port
- 12. Timers/Counters
- 13. Timer 2
- 14. WatchDog Timer
- 15. Atmel CAN Controller
- 15.1. Introduction
- 15.2. CAN Controller Description
- 15.3. CAN Controller Mailbox and Registers Organization
- 15.4. IT CAN management
- 15.5. Bit Timing and BaudRate
- 15.6. Fault Confinement
- 15.7. Acceptance filter
- 15.8. Data and Remote frame
- 15.9. Time Trigger Communication (TTC) and Message Stamping
- 15.10. CAN Autobaud and Listening mode
- 15.11. CAN SFR’s
- 15.12. Registers
- 16. Programmable Counter Array PCA
- 17. Analog-to-Digital Converter (ADC)
- 18. Interrupt System
- 19. Electrical Characteristics
- 20. Ordering Information
120 Rev.A - May 17, 2001
Preliminary
T89C51CC02
ADCLK (S:F2h)
ADC Clock Prescaler
Reset Value: XXX0 0000b
Figure 123. ADCLK Register
ADDH (S:F5h Read Only)
ADC Data High byte register
Reset Value: 00h
Figure 124. ADDH Register
ADDL (S:F4h Read Only)
ADC Data Low byte register
Reset Value: 00h
Figure 125. ADDL Register
7 6 5 4 3 2 1 0
- - - PRS 4 PRS 3 PRS 2 PRS 1 PRS 0
Bit Number Bit Mnemonic Description
7-5 -
Reserved
The value read from these bits are indeterminate. Do not set these bits.
4-0 PRS4:0
Clock Prescaler
f
ADC
= fosc / (4 (or 2 in X2 mode)* PRS)
7 6 5 4 3 2 1 0
ADAT 9 ADAT 8 ADAT 7 ADAT 6 ADAT 5 ADAT 4 ADAT 3 ADAT 2
Bit Number Bit Mnemonic Description
7-0 ADAT9:2
ADC result
bits 9-2
7 6 5 4 3 2 1 0
------ADAT 1 ADAT 0
Bit Number Bit Mnemonic Description
7-2 -
Reserved
The value read from these bits are indeterminate. Do not set these bits.
1-0 ADAT1:0
ADC result
bits 1-0