Owner's manual
Table Of Contents
- 8-bit MCU with CAN controller and Flash
- 1. Description
- 2. Features
- 3. Block Diagram
- 4. Pin Configuration
- 5. SFR Mapping
- 6. Clock
- 7. Program/Code Memory
- 8. Data Memory
- 9. EEPROM data memory
- 10. In-System-Programming (ISP)
- 11. Serial I/O Port
- 12. Timers/Counters
- 13. Timer 2
- 14. WatchDog Timer
- 15. Atmel CAN Controller
- 15.1. Introduction
- 15.2. CAN Controller Description
- 15.3. CAN Controller Mailbox and Registers Organization
- 15.4. IT CAN management
- 15.5. Bit Timing and BaudRate
- 15.6. Fault Confinement
- 15.7. Acceptance filter
- 15.8. Data and Remote frame
- 15.9. Time Trigger Communication (TTC) and Message Stamping
- 15.10. CAN Autobaud and Listening mode
- 15.11. CAN SFR’s
- 15.12. Registers
- 16. Programmable Counter Array PCA
- 17. Analog-to-Digital Converter (ADC)
- 18. Interrupt System
- 19. Electrical Characteristics
- 20. Ordering Information
Rev.A - May 17, 2001 109
Preliminary
T89C51CC02
16.7. PCA Registers
CMOD (S:D8h)
PCA Counter Mode Register
Reset Value = 00XX X000b
Figure 110. CMOD Register
7 6 5 4 3 2 1 0
CIDL WDTE - - - CPS1 CPS0 ECF
Bit Number Bit Mnemonic Description
7 CIDL
PCA Counter Idle Control bit
Clear to let the PCA run during Idle mode.
Set to stop the PCA when Idle mode is invoked.
6 WDTE
Watchdog Timer Enable
Clear to disable Watchdog Timer function on PCA Module 4,
Set to enable it.
5-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2 CPS1
EWC Count Pulse Select bits
CPS1 CPS0 Clock source
0 0 Internal Clock, FPca/6
0 1 Internal Clock, FPca/2
1 0 Timer 0 overflow
1 1 External clock at ECI/P1.2 pin (Max. Rate = FPca/4)
1 CPS0
0 ECF
Enable PCA Counter Overflow Interrupt bit
Clear to disable CF bit in CCON register to generate an interrupt.
Set to enable CF bit in CCON register to generate an interrupt.