Owner's manual
Table Of Contents
- 8-bit MCU with CAN controller and Flash
- 1. Description
- 2. Features
- 3. Block Diagram
- 4. Pin Configuration
- 5. SFR Mapping
- 6. Clock
- 7. Program/Code Memory
- 8. Data Memory
- 9. EEPROM data memory
- 10. In-System-Programming (ISP)
- 11. Serial I/O Port
- 12. Timers/Counters
- 13. Timer 2
- 14. WatchDog Timer
- 15. Atmel CAN Controller
- 15.1. Introduction
- 15.2. CAN Controller Description
- 15.3. CAN Controller Mailbox and Registers Organization
- 15.4. IT CAN management
- 15.5. Bit Timing and BaudRate
- 15.6. Fault Confinement
- 15.7. Acceptance filter
- 15.8. Data and Remote frame
- 15.9. Time Trigger Communication (TTC) and Message Stamping
- 15.10. CAN Autobaud and Listening mode
- 15.11. CAN SFR’s
- 15.12. Registers
- 16. Programmable Counter Array PCA
- 17. Analog-to-Digital Converter (ADC)
- 18. Interrupt System
- 19. Electrical Characteristics
- 20. Ordering Information
100 Rev.A - May 17, 2001
Preliminary
T89C51CC02
CANSTMPH (S:AFh Read Only)
CAN Stamp Timer High
No default value after reset
Figure 100. CANSTMPH Register
CANSTMPL (S:AEh Read Only)
CAN Stamp Timer Low
No default value after reset
Figure 101. CANSTMPL Register
CANTTCH (S:A5h Read Only)
CAN TTC Timer High
Reset Value: 0000 0000b
Figure 102. CANTTCH Register
7 6 5 4 3 2 1 0
TIMSTMP 15 TIMSTMP 14 TIMSTMP 13 TIMSTMP 12 TIMSTMP 11 TIMSTMP 10 TIMSTMP 9 TIMSTMP 8
Bit Number Bit Mnemonic Description
7-0 TIMSTMP15:8
High byte of Time Stamp
See Figure 63.
7 6 5 4 3 2 1 0
TIMSTMP 7 TIMSTMP 6 TIMSTMP 5 TIMSTMP 4 TIMSTMP 3 TIMSTMP 2 TIMSTMP 1 TIMSTMP 0
Bit Number Bit Mnemonic Description
7-0 TIMSTMP7:0
Low byte of Time Stamp
See Figure 63.
7 6 5 4 3 2 1 0
TIMTTC 15 TIMTTC 14 TIMTTC 13 TIMTTC 12 TIMTTC 11 TIMTTC 10 TIMTTC 9 TIMTTC 8
Bit Number Bit Mnemonic Description
7-0 TIMTTC15:8
High byte of TTC Timer
See Figure 63.