Manual

ManualsBrandsRainbow Electronics ManualsSensorsT89C51CC01

Rev. D – 17-Dec-01

1. Features

• 80C51 core architecture:

– 256 bytes of on-chip RAM

– 1 Kbytes of on-chip ERAM

– 32 Kbytes of on-chip Flash memory

Data Retention: 10 years at 85°C

Read/Write cycle: 10k

– 2 Kbytes of on-chip Flash for Bootloader

– 2 Kbytes of on-chip EEPROM

Read/Write cycle: 100k

– 14-sources 4-level interrupts

– Three 16-bit timers/counters

– Full duplex UART compatible 80C51

– Maximum crystal frequency 40 MHz. In X2 mode, 20 MHz (CPU core, 40 MHz)

– Five ports: 32 + 2 digital I/O lines

– Five-channel 16-bit PCA with:

PWM (8-bit)

High-speed output

Timer and edge capture

– Double Data Pointer

– 21-bit watchdog timer (7 programmable bits)

• A 10-bit resolution analog to digital converter (ADC) with 8 multiplexed inputs

• Full CAN controller:

– Fully compliant with CAN rev2.0A and 2.0B

– Optimized structure for communication management (via SFR)

– 15 independent message objects:

Each message object programmable on transmission or reception

individual tag and mask filters up to 29-bit identifier/channel

8-byte cyclic data register (FIFO)/message object

16-bit status & control register/message object

16-bit Time-Stamping register/message object

CAN specification 2.0 part A or 2.0 part B programmable for each message

object

Access to message object control and data registers via SFR

Programmable reception buffer length up to 15 message objects

Priority management of reception of hits on several message objects at the

same time (Basic CAN Feature)

Priority management for transmission

message object overrun interrupt

– Supports

Time Triggered Communication

Autobaud and Listening mode

Programmable Automatic reply mode

– 1 Mbit/s maximum transfer rate at 8MHz* Crystal frequency in X2 mode.

– Readable error counters

– Programmable link to on-chip Timer for Time Stamping and Network

synchronization

– Independent baud rate prescaler

– Data, Remote, Error and overload frame handling

• On-chip emulation Logic (enhanced Hook system)

• Power saving modes:

– Idle mode

– Power down mode

• Power supply: 5V +/- 10% (or 3V** +/- 10%)

• Temperature range: Industrial (-40° to +85°C)

• Packages: VQFP44, PLCC44, CA-BGA64

Note:

* At BRP = 1 sampling point will be fixed.

** Ask for availability

Enhanced 8-bit

MCU with CAN

controller and

Flash

T89C51CC01

Summary of content (149 pages)

PAGE 1
. Features • 80C51 core architecture: – 256 bytes of on-chip RAM – 1 Kbytes of on-chip ERAM – 32 Kbytes of on-chip Flash memory Data Retention: 10 years at 85°C Read/Write cycle: 10k – 2 Kbytes of on-chip Flash for Bootloader – 2 Kbytes of on-chip EEPROM Read/Write cycle: 100k – 14-sources 4-level interrupts – Three 16-bit timers/counters – Full duplex UART compatible 80C51 – Maximum crystal frequency 40 MHz.
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. Description The T89C51CC01 is the first member of the CANaryTM family of 8-bit microcontrollers dedicated to CAN network applications. In X2 mode a maximum external clock rate of 20 MHz reaches a 300 ns cycle time. Besides the full CAN controller T89C51CC01 provides 32 Kbytes of Flash memory including In-System Programming (ISP), 2Kbytes Boot Flash Memory, 2 Kbytes EEPROM and 1.2 Kbyte RAM. Primary attention is paid to the reduction of the electro-magnetic emission of T89C51CC01.
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T89C51CC01 6 5 4 3 2 1 44 43 42 41 40 P1.3 / AN3 / CEX0 P1.2 / AN2 / ECI P1.1 / AN1 / T2EX P1.0 / AN 0 / T2 VAREF VAGND RESET VSS VCC XTAL1 XTAL2 4. Pin Configuration 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 PLCC44 ALE PSEN P0.7 / AD7 P0.6 / AD6 P0.5 / AD5 P0.4 / AD4 P0.3 / AD3 P0.2 / AD2 P0.1 / AD1 P0.0 / AD0 P2.0 / A8 P1.3 / AN3 / CEX0 P1.2 / AN2 / ECI P1.1 / AN1 / T2EX P1.0 / AN 0 / T2 VAREF VAGND RESET VSS VCC XTAL1 XTAL2 P3.6 / WR P3.7 / RD P4.0/ TxDC P4.1 / RxDC P2.
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1 2 3 4 5 6 7 8 A P1.4/AN4 P1.2/AN2 P1.0/AN0 VAGND VSS VSS XTAL1 B P1.5/AN5 P1.3/AN3 P1.1/AN1 VAREF VDD VDD NC ALE C P1.7/AN7 P1.6/AN6 NC NC NC NC PSEN P0.7 D EA NC NC NC NC P0.6 P0.5 E P3.0 P3.1 NC NC NC NC P0.2 P0.4 F P3.2 P3.3 NC NC NC NC P0.1 P0.3 G P3.4 P3.5 P4.0 P4.1 P2.4 P2.2 NC P0.0 P3.6 P3.7 P2.7 P2.6 P2.5 P2.3 P2.1 P2.0 H RESET XTAL2 CA-BGA64 Top View 4 T89C51CC01 Rev.
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T89C51CC01 Table 1. Pin Description Pin Name Type VSS GND VCC Description Circuit ground. Supply Voltage. VAREF Reference Voltage for ADC VAGND Reference Ground for ADC P0.0:7 I/O Port 0: Is an 8-bit open drain bi-directional I/O port. Port 0 pins that have 1’s written to them float, and in this state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external Program and Data Memory.
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Pin Name Type Description Port 3: Is an 8-bit bi-directional I/O port with internal pull-ups. Port 3 pins that have 1’s written to them are pulled high by the internal pull-up transistors and can be used as inputs in this state. As inputs, Port 3 pins that are being pulled low externally will be a source of current (IIL , see section "Electrical Characteristic") because of the internal pull-ups.
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T89C51CC01 Pin Name Type Description RESET I/O Reset: A high level on this pin during two machine cycles while the oscillator is running resets the device. An internal pull-down resistor to VSS permits power-on reset using only an external capacitor to VCC. ALE O ALE: An Address Latch Enable output for latching the low byte of the address during accesses to the external memory. The ALE is activated every 1/6 oscillator periods (1/3 in X2 mode) except during an external data memory access.
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Figure 1. Port 1, Port 3 and Port 4 Structure VCC ALTERNATE OUTPUT FUNCTION READ LATCH INTERNAL BUS WRITE TO LATCH 4.4 Port 0 and Port2 P1.x P3.x P4.x D P1.X Q P3.X P4.X LATCH CL READ PIN Note: INTERNAL PULL-UP (1) ALTERNATE INPUT FUNCTION The internal pull-up can be disabled on P1 when analog function is selected. Ports 0 and 2 are used for general-purpose I/O or as the external address/data bus. Port 0, shown in Figure 3, differs from the other Ports in not having internal pull-ups.
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T89C51CC01 Figure 3. Port 2 Structure ADDRESS HIGH/ CONTROL VDD INTERNAL PULL-UP (2) READ LATCH P2.x (1) 1 INTERNAL BUS WRITE TO LATCH D P2.X LATCH 0 Q READ PIN Notes: 1. Port 2 is precluded from use as general purpose I/O Ports when as address/data bus drivers. 2. Port 2 internal strong pull-ups FET (P1 in FiGURE) assist the logic-one output for memory bus cycle.
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It is not obvious the last three instructions in this list are Read-Modify-Write instructions. These instructions read the port (all 8 bits), modify the specifically addressed bit and write the new byte back to the latch. These Read-Modify-Write instructions are directed to the latch rather than the pin in order to avoid possible misinterpretation of voltage (and therefore, logic) levels at the pin.
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T89C51CC01 5. SFR Mapping The Special Function Registers (SFRs) of the T89C51CC01 fall into the following categories: Table 2. C51 Core SFRs Mnemonic Add Name ACC E0h Accumulator B F0h B Register PSW D0h Program Status Word SP 81h Stack Pointer DPL Data Pointer Low 82h byte LSB of DPTR DPH Data Pointer High 83h byte MSB of DPTR 7 6 5 4 3 2 1 0 CY AC F0 RS1 RS0 OV F1 P 1 0 Table 3.
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Mnemonic Add Name 7 6 5 4 3 2 1 0 T2CON C8h Timer/Counter 2 control TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2# T2MOD C9h Timer/Counter 2 Mode - - - - - - T2OE DCEN RCAP2H Timer/Counter 2 CBh Reload/Capture High byte RCAP2L Timer/Counter 2 CAh Reload/Capture Low byte WDTRST A6h WatchDog Timer Reset WDTPRG A7h WatchDog Timer Program - - - - - S2 S1 S0 Table 5.
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T89C51CC01 Mnemonic Add Name 7 6 5 4 3 2 1 0 FAh PCA Compare Capture Module 1 H CCAP0H7 CCAP0H6 CCAP0H5 CCAP0H4 CCAP0H3 CCAP0H2 CCAP0H1 CCAP0H0 PCA Compare Capture Module 2 H CCAP1H7 CCAP1H6 CCAP1H5 CCAP1H4 CCAP1H3 CCAP1H2 CCAP1H1 CCAP1H0 CCAP2H7 CCAP2H6 CCAP2H5 CCAP2H4 CCAP2H3 CCAP2H2 CCAP2H1 CCAP2H0 CCAP3H7 CCAP3H6 CCAP3H5 CCAP3H4 CCAP3H3 CCAP3H2 CCAP3H1 CCAP3H0 CCAP4H7 CCAP4H6 CCAP4H5 CCAP4H4 CCAP4H3 CCAP4H2 CCAP4H1 CCAP4H0 CCAP0L7 CCAP0L6 CCAP0L5 C
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Table 9.
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T89C51CC01 Mnemonic Add CANCONH B3h CAN Control Channel CANMSG A3h CAN Message Data CANIDT1 CANIDT2 CANIDT3 CANIDT4 CANIDM1 CANIDM2 CANIDM3 CANIDM4 BCh BDh BEh BFh C4h C5h C6h C7h Name CAN Identifier Tag byte 1(Part A) CAN Identifier Tag byte 1(PartB) CAN Identifier Tag byte 2 (PartA) CAN Identifier Tag byte 2 (PartB) CAN Identifier Tag byte 3(PartA) CAN Identifier Tag byte 3(PartB) CAN Identifier Tag byte 4(PartA) CAN Identifier Tag byte 4(PartB) CAN Identifier Mask byte 1(PartA) CAN
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Table 11.
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T89C51CC01 6. Clock The T89C51CC01 core needs only 6 clock periods per machine cycle. This feature, called”X2”, provides the following advantages: • Divides frequency crystals by 2 (cheaper crystals) while keeping the same CPU power. • Saves power consumption while keeping the same CPU power (oscillator power saving). • Saves power consumption by dividing dynamic operating frequency by 2 in operating and idle modes. • Increases CPU power by 2 while keeping the same crystal frequency.
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Figure 5. Clock CPU Generation Diagram X2B Hardware byte PCON.0 On RESET IDL X2 CKCON.0 ÷2 XTAL1 CPU Core Clock 0 1 XTAL2 CPU CLOCK PD CPU Core Clock Symbol and ADC PCON.1 ÷2 1 FT0 Clock 0 ÷2 1 FT1 Clock 0 ÷2 1 FT2 Clock 0 ÷2 1 FUart Clock 0 ÷2 1 FPca Clock 0 ÷2 1 FWd Clock 0 ÷2 1 FCan Clock 0 PERIPH CLOCK X2 CKCON.0 Peripheral Clock Symbol 18 CANX2 WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 CKCON.7 CKCON.6 CKCON.5 CKCON.4 CKCON.3 CKCON.2 CKCON.1 T89C51CC01 Rev.
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T89C51CC01 Figure 6. Mode Switching Waveforms XTAL1 XTAL2 X2 bit CPU STD X2 Note: 6.2 Register STD In order to prevent any incorrect operation while operating in the X2 mode, users must be aware that all peripherals using the clock frequency as a time reference (UART, timers...) will have their time reference divided by two. For example a free running timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms. A UART with a 4800 baud rate will have a 9600 baud rate.
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Bit Number Bit Mnemonic 1 T0X2 0 Notes: X2 Description Timer0 clock (1) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. CPU clock Clear to select 12 clock periods per machine cycle (STD mode) for CPU and all the peripherals. Set to select 6 clock periods per machine cycle (X2 mode) and to enable the individual peripherals "X2"bits. 1.
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T89C51CC01 7. Data Memory The T89C51CC01 provides data memory access in two different spaces: 1. The internal space mapped in three separate segments: • the lower 128 bytes RAM segment. • the upper 128 bytes RAM segment. • the expanded 1024 bytes RAM segment (ERAM). 2. The external space. A fourth internal segment is available but dedicated to Special Function Registers, SFRs, (addresses 80h to FFh) accessible by direct addressing mode.
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7.1 Internal Space 7.1.1 Lower 128 Bytes RAM The lower 128 bytes of RAM (see Figure 2) are accessible from address 00h to 7Fh using direct or indirect addressing modes. The lowest 32 bytes are grouped into 4 banks of 8 registers (R0 to R7). Two bits RS0 and RS1 in PSW register (see Figure 3) select which bank is in use according to Table 1.
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T89C51CC01 7.2 External Space 7.2.1 Memory Interface The external memory interface comprises the external bus (port 0 and port 2) as well as the bus control signals (RD#, WR#, and ALE). Figure 4 shows the structure of the external address bus. P0 carries address A7:0 while P2 carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 2 describes the external memory interface signals. Figure 4.
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For simplicity, the accompanying figures depict the bus cycle waveforms in idealized form and do not provide precise timing information. For bus cycle timing parameters refer to the Section “AC Characteristics” of the T89C51CC01 datasheet. Figure 5. External Data Read Waveforms CPU Clock ALE RD#1 P0 P2 Notes: DPL or Ri P2 D7:0 DPH or P22 1. RD# signal may be stretched using M0 bit in AUXR register. 2. When executing MOVX @Ri instruction, P2 outputs SFR content. Figure 6.
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T89C51CC01 Figure 7. Dual Data Pointer Implementation DPL0 0 DPL1 1 DPL DPTR0 DPS DPTR1 DPH0 0 DPH1 1 AUXR1.0 DPTR DPH 7.3.2 Application Software can take advantage of the additional data pointers to both increase speed and reduce code size, for example, block operations (copy, compare…) are well served by using one data pointer as a “source” pointer and the other one as a “destination” pointer.
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7.4 Registers Table 3. PSW Register PSW (S:8Eh) Program Status Word Register. 7 6 5 4 3 2 1 0 CY AC F0 RS1 RS0 OV F1 P Bit Number Bit Mnemonic 7 CY Carry Flag Carry out from bit 1 of ALU operands. 6 AC Auxiliary Carry Flag Carry out from bit 1 of addition operands. 5 F0 User Definable Flag 0. 4-3 RS1:0 2 OV Overflow Flag Overflow set by arithmetic operations. 1 F1 User Definable Flag 1. 0 P Parity Bit Set when ACC contains an odd number of 1’s.
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T89C51CC01 Bit Number 3-2 1 0 Bit Mnemonic XRS1-0 EXTRAM A0 Description ERAM size: Accessible size of the ERAM XRS1:0 ERAM size 0 0 256 bytes 0 1 512 bytes 1 0 768 bytes 1 1 1024 bytes (default) Internal/External RAM (00h - FFh) access using MOVX @ Ri / @ DPTR 0 - Internal ERAM access using MOVX @ Ri / @ DPTR. 1 - External data memory access.
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8. EEPROM Data Memory The 2k byte on-chip EEPROM memory block is located at addresses 0000h to 07FFh of the XRAM/ERAM memory space and is selected by setting control bits in the EECON register. A read in the EEPROM memory is done with a MOVX instruction. A physical write in the EEPROM memory is done in two steps: write data in the column latches and transfer of all data latches into an EEPROM memory row (programming). The number of data written on the page may vary from 1 up to 128 bytes (the page size).
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T89C51CC01 8.4 Examples ;*F************************************************************************* ;* NAME: api_rd_eeprom_byte ;* DPTR contain address to read.
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8.5 Registers Table 6. EECON Register EECON (S:0D2h) EEPROM Control Register 7 6 5 4 3 2 1 0 EEPL3 EEPL2 EEPL1 EEPL0 - - EEE EEBUSY Bit Number Bit Mnemonic 7-4 EEPL3-0 Programming Launch command bits Write 5Xh followed by AXh to EEPL to launch the programming. 3 - Reserved The value read from this bit is indeterminate. Do not set this bit. 2 - Reserved The value read from this bit is indeterminate. Do not set this bit.
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T89C51CC01 9. Program/Code Memory The T89C51CC01 implement 32 Kbytes of on-chip program/code memory. Figure 8 shows the partitioning of internal and external program/code memory spaces depending on the product. The FLASH memory increases EPROM and ROM functionality by in-circuit electrical erasure and programming. Thanks to the internal charge pump, the high voltage needed for programming or erasing FLASH cells is generated on-chip using the standard VDD voltage.
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Figure 9. External Code Memory Interface Structure FLASH EPROM T89C51CC01 A15:8 P2 A15:8 ALE AD7:0 P0 Latch A7:0 A7:0 D7:0 PSEN# OE Table 7. External Code Memory Interface Signals 9.1.2 External Bus Cycles Signal Name Type Alternate Function A15:8 O AD7:0 I/O ALE O Address Latch Enable ALE signals indicates that valid address information are available on lines AD7:0.
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T89C51CC01 Figure 10. External Code Fetch Waveforms CPU Clock ALE PSEN# P0 D7:0 PCL P2 PCH 9.2 FLASH Memory Architecture D7:0 PCH PCL D7:0 PCH T89C51CC01 features two on-chip flash memories: • Flash memory FM0: containing 32 Kbytes of program memory (user space) organized into 128 byte pages, • Flash memory FM1: 2 Kbytes for boot loader and Application Programming Interfaces (API).
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9.2.1 FM0 Memory Architecture The flash memory is made up of 4 blocks (see Figure 11): 3. The memory array (user space) 32 Kbytes 4. The Extra Row 5. The Hardware security bits 6. The column latch registers User Space This space is composed of a 32 Kbytes FLASH memory organized in 256 pages of 128 bytes. It contains the user’s application code. Extra Row (XRow) This row is a part of FM0 and has a size of 128 bytes. The extra row may contain information for boot loader usage.
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T89C51CC01 9.3 Overview of FM0 operations The CPU interfaces to the flash memory through the FCON register and AUXR1 register. These registers are used to: 9.3.1 Mapping of the memory space • Map the memory spaces in the adressable space • Launch the programming of the memory spaces • Get the status of the flash memory (busy/not busy) By default, the user space is accessed by MOVC instruction for read only. The column latches space is made accessible by setting the FPS bit in FCON register.
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Table 10.
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T89C51CC01 Figure 12. Column Latches Loading Procedure Column Latches Loading Save & Disable IT EA= 0 Column Latches Mapping FCON = 08h (FPS=1) Data Load DPTR= Address ACC= Data Exec: MOVX @DPTR, A Last Byte to load? Data memory Mapping FCON = 00h (FPS = 0) Restore IT Note: The last page address used when loading the column latch is the one used to select the page programming address. 9.3.
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• Launch the programming by writing the data sequence 52h followed by A2h in FCON register (only from FM1). The end of the programming indicated by the FBUSY flag cleared. • Enable the interrupts. Figure 13.
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T89C51CC01 Figure 14. Hardware Programming Procedure FLASH Spaces Programming Save & Disable IT EA= 0 Save & Disable IT EA= 0 FCON = 0Ch Launch Programming FCON= 54h FCON= A4h Data Load DPTR= 00h ACC= Data Exec: MOVX @DPTR, A FBusy Cleared? End Loading Restore IT Clear Mode FCON = 00h End Programming RestoreIT 9.3.7 Reading the FLASH Spaces User The following procedure is used to read the User space: • Read one byte in Accumulator by executing MOVC A,@A+DPTR with A+DPTR=read@.
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Figure 15. Reading Procedure FLASH Spaces Reading FLASH Spaces Mapping FCON= 00000xx0b Data Read DPTR= Address ACC= 0 Exec: MOVC A, @A+DPTR Clear Mode FCON = 00h 9.3.8 Flash Protection from Parallel Programming The three lock bits in Hardware Security Byte (see "In-System Programming" section) are programmed according to Table 11 provide different level of protection for the onchip code and data located in FM0 and FM1. The only way to write this bits are the parallel mode.
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T89C51CC01 9.4 Registers FCON RegisterFCON (S:D1h) FLASH Control Register 7 6 5 4 3 2 1 0 FPL3 FPL2 FPL1 FPL0 FPS FMOD1 FMOD0 FBUSY Bit Number Bit Mnemonic 7-4 FPL3:0 3 FPS 2-1 FMOD1:0 0 FBUSY Description Programming Launch Command Bits Write 5Xh followed by AXh to launch the programming according to FMOD1:0. (see Table 10.) FLASH Map Program Space Set to map the column latch space in the data memory space. Clear to re-map the data memory space. FLASH Mode See Table 9 or Table 10.
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10. In-SystemProgramming (ISP) With the implementation of the User Space (FM0) and the Boot Space (FM1) in Flash technology the T89C51CC01 allows the system engineer the development of applications with a very high level of flexibility. This flexibility is based on the possibility to alter the customer program at any stages of a product’s life: • Before assembly the 1st personalization of the product by programming in the FM0 and if needed also a customized Boot loader in the FM1.
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T89C51CC01 10.2 Boot Process 10.2.1 Software boot process example Many algorithms can be used for the software boot process. Before describing them, We give below the description of the different flags and bytes. Boot Loader Jump Bit (BLJB): - This bit indicates if on RESET the user wants to jump to this application at address @0000h on FM0 or execute the boot loader at address @F800h on FM1. - BLJB = 0 on parts delivered with bootloader programmed. - To read or modify this bit, the APIs are used.
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Figure 17. Hardware Boot Process Algorithm bit ENBOOT in AUXR1 register is initialized with BLJB. RESET Hardware Hardware condition? No ENBOOT = 0 PC = 0000h Yes ENBOOT = 1 PC = F800h FCON = 00h FCON = F0h BLJB == 0 ? No Yes Software ENBOOT = 1 PC = F800h 10.3 ApplicationProgramming-Interface Application in FM0 Boot Loader in FM1 Several Application Program Interface (API) calls are available for use by an application program to permit selective erasing and programming of FLASH pages.
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T89C51CC01 Table 12.
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10.5 Hardware Security Byte Table 14. Hardware Security byte 7 6 5 4 3 2 1 0 X2B BLJB - - - LB2 LB1 LB0 Bit Number Bit Mnemonic 7 X2B X2 Bit Set this bit to start in standard mode Clear this bit to start in X2 mode. 6 BLJB Boot Loader JumpBit - 1: To start the user’s application on next RESET (@0000h) located in FM0, - 0: To start the boot loader(@F800h) located in FM1. 5-3 - 2-0 LB2:0 Description Reserved The value read from these bits are indeterminate.
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T89C51CC01 11. Serial I/O Port The T89C51CC01 I/O serial port is compatible with the I/O serial port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as a Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3).
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valid stop bits cannot clear the FE bit. When the FE feature is enabled, RI rises on the stop bit instead of the last data bit (See Figure 20. and Figure 21.). Figure 20. UART Timing in Mode 1 RXD D0 D1 D2 D3 D4 D5 D6 D7 Data byte Start bit Stop bit RI SMOD0=X FE SMOD0=1 Figure 21. UART Timing in Modes 2 and 3 RXD D0 Start bit D1 D2 D3 D4 Data byte D5 D6 D7 D8 Ninth Stop bit bit RI SMOD0=0 RI SMOD0=1 FE SMOD0=1 11.
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T89C51CC01 11.3 Given Address Each device has an individual address that is specified in the SADDR register; the SADEN register is a mask byte that contains don’t-care bits (defined by zeros) to form the device’s given address. The don’t-care bits provide the flexibility to address one or more slaves at a time. The following example illustrates how a given address is formed. To address a device by its individual address, the SADEN mask byte must be 1111 1111b.
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For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the master must send an address FFh. To communicate with slaves A and B, but not slave C, the master can send and address FBh. 11.5 Registers Table 15.
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T89C51CC01 Table 16. SADEN Register SADEN (S:B9h) Slave Address Mask Register 7 6 Bit Number Bit Mnemonic 7-0 5 4 3 2 1 0 2 1 0 2 1 0 Description Mask Data for Slave Individual Address Reset Value = 0000 0000b Not bit addressable Table 17. SADDR Register SADDR (S:A9h) Slave Address Register 7 6 Bit Number Bit Mnemonic 7-0 5 4 3 Description Slave Individual Address Reset Value = 0000 0000b Not bit addressable Table 18.
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Table 19. PCON Register PCON (S:87h) Power Control Register 7 6 5 4 3 2 1 0 SMOD1 SMOD0 - POF GF1 GF0 PD IDL Bit Number Bit Mnemonic 7 SMOD1 Serial port Mode bit 1 Set to select double baud rate in mode 1, 2 or 3. 6 SMOD0 Serial port Mode bit 0 Clear to select SM0 bit in SCON register. Set to select FE bit in SCON register. 5 - Description Reserved The value read from this bit is indeterminate. Do not set this bit. 4 POF Power-Off Flag Clear to recognize next reset type.
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T89C51CC01 12. Timers/Counters The T89C51CC01 implements two general-purpose, 16-bit Timers/Counters. Such are identified as Timer 0 and Timer 1, and can be independently configured to operate in a variety of modes as a Timer or an event Counter. When operating as a Timer, the Timer/Counter runs for a programmed length of time, then issues an interrupt request. When operating as a Counter, the Timer/Counter counts negative transitions on an external pin.
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Figure 22. Timer/Counter x (x= 0 or 1) in Mode 0 see section “Clock” FTx CLOCK ÷6 0 THx (8 bits) 1 TLx (5 bits) Overflow TFx TCON reg Tx Timer x Interrupt Request C/Tx# TMOD reg INTx# GATEx TRx TMOD reg 12.2.2 Mode 1 (16-bit Timer) TCON reg Mode 1 configures Timer 0 as a 16-bit Timer with TH0 and TL0 registers connected in cascade (see Figure 23). The selected input increments TL0 register. Figure 23.
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T89C51CC01 12.2.4 Mode 3 (Two 8-bit Timers) Mode 3 configures Timer 0 such that registers TL0 and TH0 operate as separate 8-bit Timers (see Figure 25). This mode is provided for applications requiring an additional 8bit Timer or Counter. TL0 uses the Timer 0 control bits C/T0# and GATE0 in TMOD register, and TR0 and TF0 in TCON register in the normal manner. TH0 is locked into a Timer function (counting FPER /6) and takes over use of the Timer 1 interrupt (TF1) and run control (TR1) bits.
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12.3.1 Mode 0 (13-bit Timer) Mode 0 configures Timer 1 as a 13-bit Timer, which is set up as an 8-bit Timer (TH1 register) with a modulo-32 prescaler implemented with the lower 5 bits of the TL1 register (see Figure 22). The upper 3 bits of TL1 register are ignored. Prescaler overflow increments TH1 register. 12.3.2 Mode 1 (16-bit Timer) Mode 1 configures Timer 1 as a 16-bit Timer with TH1 and TL1 registers connected in cascade (see Figure 23). The selected input increments TL1 register. 12.3.
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T89C51CC01 12.5 Registers Table 20. TCON Register TCON (S:88h) Timer/Counter Control Register 7 6 5 4 3 2 1 0 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Bit Number Bit Mnemonic 7 TF1 Timer 1 Overflow Flag Cleared by hardware when processor vectors to interrupt routine. Set by hardware on Timer/Counter overflow, when Timer 1 register overflows. 6 TR1 Timer 1 Run Control Bit Clear to turn off Timer/Counter 1. Set to turn on Timer/Counter 1.
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Table 21. TMOD Register TMOD (S:89h) Timer/Counter Mode Control Register. 7 6 5 4 3 2 1 0 GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00 Bit Number Bit Mnemonic 7 GATE1 Timer 1 Gating Control Bit Clear to enable Timer 1 whenever TR1 bit is set. Set to enable Timer 1 only while INT1# pin is high and TR1 bit is set. 6 C/T1# Timer 1 Counter/Timer Select Bit Clear for Timer operation: Timer 1 counts the divided-down system clock.
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T89C51CC01 Table 22. TH0 Register TH0 (S:8Ch) Timer 0 High Byte Register. 7 6 Bit Number Bit Mnemonic 7:0 5 4 3 2 1 0 2 1 0 2 1 0 Description High Byte of Timer 0. Reset Value= 0000 0000b Table 23. TL0 Register TL0 (S:8Ah) Timer 0 Low Byte Register. 7 6 Bit Number Bit Mnemonic 7:0 5 4 3 Description Low Byte of Timer 0. Reset Value= 0000 0000b Table 24. TH1 Register TH1 (S:8Dh) Timer 1 High Byte Register.
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Table 25. TL1 Register TL1 (S:8Bh) Timer 1 Low Byte Register. 7 6 Bit Number Bit Mnemonic 7:0 5 4 3 2 1 0 Description Low Byte of Timer 1. Reset Value= 0000 0000b 60 T89C51CC01 Rev.
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T89C51CC01 13. Timer 2 The T89C51CC01 timer 2 is compatible with timer 2 in the 80C52. It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2 that are cascade- connected. It is controlled by T2CON register (See Table ) and T2MOD register (See Table 28). Timer 2 operation is similar to Timer 0 and Timer 1. C/T2 selects F T2 clock/6 (timer operation) or external pin T2 (counter operation) as timer clock.
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Figure 27. Auto-Reload Mode Up/Down Counter see section “Clock” FT2 CLOCK :6 0 1 TR2 T2CON.2 CT/2 T2CON.1 T2 (DOWN COUNTING RELOAD VALUE) FFh (8-bit) FFh (8-bit) T2EX: 1=UP 2=DOWN TOGGLE T2CONreg EXF2 TL2 (8-bit) TH2 (8-bit) TIMER 2 INTERRUPT TF2 T2CONreg RCAP2L (8-bit) RCAP2H (8-bit) (UP COUNTING RELOAD VALUE) 13.2 Programmable Clock-Output In clock-out mode, timer 2 operates as a 50%-duty-cycle, programmable clock generator (See Figure 28).
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T89C51CC01 It is possible to use timer 2 as a baud rate generator and a clock generator simultaneously. For this configuration, the baud rates and clock frequencies are not independent since both functions use the values in the RCAP2H and RCAP2L registers. Figure 28. Clock-Out Mode FT2 CLOCK 0 1 TR2 T2CON.2 CT/2 TL2 (8-bit) TH2 (8-bit) T2CON.1 OVERFLOW RCAP2L RCAP2H (8-bit) (8-bit) T2 1 0 :2 C/T2 T2OE T2CON reg T2MOD reg T2EX EXF2 EXEN2 T2CON reg TIMER 2 INTERRUPT T2CON reg 63 Rev.
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13.3 Registers Table 26. T2CON Register T2CON (S:C8h) Timer 2 Control Register 7 6 5 4 3 2 1 0 TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2# Bit Number Bit Mnemonic 7 TF2 Description Timer 2 overflow Flag TF2 is not set if RCLK=1 or TCLK = 1. Must be cleared by software. Set by hardware on timer 2 overflow. 6 EXF2 Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1.
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T89C51CC01 Table 27. T2MOD Register T2MOD (S:C9h) Timer 2 Mode Control Register 7 6 5 4 3 2 1 0 - - - - - - T2OE DCEN Bit Number Bit Mnemonic 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit.
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Table 29. TL2 Register TL2 (S:CCh) Timer 2 Low Byte Register 7 6 5 4 3 2 1 0 - - - - - - - - Bit Number Bit Mnemonic 7-0 Description Low Byte of Timer 2. Reset Value = 0000 0000b Not bit addressable Table 30. RCAP2H Register RCAP2H (S:CBh) Timer 2 Reload/Capture High Byte Register 7 6 5 4 3 2 1 0 - - - - - - - - Bit Number Bit Mnemonic 7-0 Description High Byte of Timer 2 Reload/Capture. Reset Value = 0000 0000b Not bit addressable Table 31.
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T89C51CC01 14. WatchDog Timer T89C51CC01 contains a powerful programmable hardware WatchDog Timer (WDT) that automatically resets the chip if it software fails to reset the WDT before the selected time interval has elapsed. It permits large Time-Out ranking from 16ms to 2s @Fosc = 12MHz in X1 mode. This WDT consists of a 14-bit counter plus a 7-bit programmable counter, a WatchDog Timer reset register (WDTRST) and a WatchDog Timer programming (WDTPRG) register.
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14.1 WatchDog Programming The three lower bits (S0, S1, S2) located into WDTPRG register permit to program the WDT duration. Table 32.
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T89C51CC01 interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Power Down. To ensure that the WDT does not overflow within a few states of exiting powerdown, it is best to reset the WDT just before entering powerdown. In the Idle mode, the oscillator continues to run.
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Table 35. WDTRST Register WDTRST (S:A6h Write only) WatchDog Timer Enable register 7 6 5 4 3 2 1 0 - - - - - - - - Bit Number Bit Mnemonic 7 - Description Watchdog Control Value Reset Value = 1111 1111b Note: 70 The WDRST register is used to reset/enable the WDT by writing 1EH then E1H in sequence without instruction between these two sequences. T89C51CC01 Rev.
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T89C51CC01 15. Atmel CAN Controller The Atmel CAN Controller provides all the features required to implement the serial communication protocol CAN as defined by BOSCH GmbH. The CAN specification as referred to by ISO/11898 (2.0A & 2.0B) for high speed and ISO/11519-2 for low speed. The CAN Controller is able to handle all types of frames (Data, Remote, Error and Overload) and achieves a bitrate of 1 Mbit/s at 8MHz1 Crystal frequency in X2 mode. Notes: 15.1 CAN Controller Description 1.
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15.2 CAN Controller Mailbox and Registers Organization The pagination allows management of the 321 registers including 300(15x20) bytes of mailbox via 34 SFR’s. All actions on the message object window SFRs apply to the corresponding message object registers pointed by the message object number find in the Page message object register (CANPAGE) as illustrate in Figure 31. Figure 31.
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T89C51CC01 15.2.1 Working on message objects The Page message object register (CANPAGE) is used to select one of the 15 message objects. Then, message object Control (CANCONCH) and message object Status (CANSTCH) are available for this selected message object number in the corresponding SFRs. A single register (CANMSG) is used for the message. The mailbox pointer is managed by the Page message object register with an auto-incrementation at the end of each access. The range of this counter is 8.
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15.3.1 Buffer mode Any message object can be used to define one buffer, including non-consecutive message objects, and with no limitation in number of message objects used up to 15. Each message object of the buffer must be initialized CONCH2 = 1 and CONCH1 = 1; Figure 32.
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T89C51CC01 Figure 33. CAN Controller interrupt structure CANGIE.5 ENRX RXOK i CANGIE.4 CANGIE.3 ENTX ENERCH CANSIT1/2 CANSTCH.5 SIT i TXOK i CANSTCH.6 CANIE1/2 BERR i EICH i CANSTCH.4 i=0 SERR i CANSTCH.3 SIT i CERR i i=14 CANSTCH.2 FERR i CANGIE.2 CANSTCH.1 ENBUF AERR i IEN1.0 ECAN CANSTCH.0 OVRBUF CANIT CANGIT.4 CANGIT.7 CANGIE.1 ENERG SERG CANGIT.3 CERG CANGIT.2 FERG CANGIT.1 IEN1.2 AERG ETIM CANGIT.0 OVRIT OVRTIM CANGIT.
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To enable an interrupt on general error: • Enable General CAN IT in the interrupt system register, • Enable interrupt on error, ENERG. To enable an interrupt on Buffer-full condition: • Enable General CAN IT in the interrupt system register, • Enable interrupt on Buffer full, ENBUF. To enable an interrupt when Timer overruns: • Enable Overrun IT in the interrupt system register. When an interrupt occurs, the corresponding message object bit is set in the SIT register.
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T89C51CC01 Figure 35.
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15.6 Fault Confinement With respect to fault confinement, a unit may be in one of the three following status: • error active, • error passive, • bus off. An error active unit takes part in bus communication and can send an active error frame when the CAN macro detects an error. An error passive unit cannot send an active error frame. It takes part in bus communication, but when an error is detected, a passive error frame is sent.
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T89C51CC01 15.7 Acceptance filter Upon a reception hit (i.e., a good comparison between the ID+RTR+RB+IDE received and an ID+RTR+RB+IDE specified while taking the comparison mask into account) the ID+RTR+RB+IDE received are written over the ID TAG Registers. ID => IDT0-29 RTR => RTRTAG RB => RB0-1TAG IDE => IDE in CANCONCH register Figure 37.
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15.
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T89C51CC01 15.9 Time Trigger Communication (TTC) and Message Stamping The T89C51CC01 has a programmable 16-bit Timer (CANTIMH&CANTIML) for message stamp and TTC. This CAN Timer starts after the CAN controller is enabled by the ENA bit in the CANGCON register.
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15.10 CAN Autobaud and To activate the Autobaud feature, the AUTOBAUD bit in the CANGCON register must be set. In this mode, the CAN controller is only listening to the line without acknowledgListening mode ing the received messages. It cannot send any message. The error flags are updated. The bit timing can be adjusted until no error occurs (good configuration find). In this mode, the error counters are frozen. To go back to the standard mode, the AUTOBAUD bit must be cleared. Figure 39.
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T89C51CC01 // Enable the CAN macro CANGCON = 02h 2.
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// Find the first message object which generate an interrupt in CANSIT1 and CANSIT2 // Select the corresponding message object // Analyse the CANSTCH register to identify which kind of interrupt is generated // Manage the interrupt // Clear the status register CANSTCH = 00h; // if it is not a channel interrupt but a general interrupt // Manage the general interrupt and clear CANGIT register // restore the old CANPAGE 84 T89C51CC01 Rev.
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T89C51CC01 15.12 CAN SFR’s Table 37.
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15.13 Registers Table 38. CANGCON Register CANGCON (S:ABh) CAN General Control Register 7 6 5 4 3 2 1 0 ABRQ OVRQ TTC SYNCTTC AUTOBAUD TEST ENA GRES Bit Number Bit Mnemonic Description ABRQ Abort request Not an auto-resetable bit. A reset of the ENCH bit (message object control & DLC register) is done for each message object.
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T89C51CC01 Table 39. CANGSTA Register CANGSTA (S:AAh) CAN General Status Register 7 6 5 4 3 2 1 0 - OVFG - TBSY RBSY ENFG BOFF ERRP Bit Number Bit Mnemonic 7 - 6 OVFG 5 - Reserved The values read from this bit is indeterminate. Do not set this bit. Overload frame flag (1) This status bit is set by the hardware as long as the produced overload frame is sent. This flag does not generate an interrupt Reserved The values read from this bit is indeterminate. Do not set this bit.
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Table 40. CANGIT Register CANGIT (S:9Bh) CAN General Interrupt 7 6 5 4 3 2 1 0 CANIT - OVRTIM OVRBUF SERG CERG FERG AERG Bit Number Bit Mnemonic 7 CANIT 6 - General interrupt flag (1) This status bit is the image of all the CAN controller interrupts sent to the interrupt controller. It can be used in the case of the polling method. Reserved The values read from this bit is indeterminate. Do not set this bit.
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T89C51CC01 Table 41. CANTEC Register CANTEC (S:9Ch Read Only) CAN Transmit Error Counter 7 6 5 4 3 2 1 0 TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 Bit Number Bit Mnemonic 7-0 TEC7:0 Description Transmit Error Counter see Figure 36 Reset Value: 00h Table 42.
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Bit Number Bit Mnemonic 2 ENBUF Enable BUF interrupt 0 - Disable 1 - Enable 1 ENERG Enable general error interrupt 0 - Disable 1 - Enable 0 - Note: Description Reserved The value read from this bit is indeterminate. Do not set this bit. see Figure 33 Reset Value: xx00 000xb Table 44.
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T89C51CC01 Table 45. CANEN2 Register CANEN2 (S:CFh Read Only) CAN Enable message object Registers 2 7 6 5 4 3 2 1 0 ENCH7 ENCH6 ENCH5 ENCH4 ENCH3 ENCH2 ENCH1 ENCH0 Bit Number Bit Mnemonic 7-0 ENCH7:0 Description Enable message object 0 - message object is disabled => the message object is free for a new emission or reception. 1 - message object is enabled. This bit is resetable by re-writing the CANCONCH of the corresponding message object. Reset Value: 0000 0000b Table 46.
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Table 47. CANSIT2 Register CANSIT2 (S:BBh Read Only) CAN Status Interrupt message object Registers 2 7 6 5 4 3 2 1 0 SIT7 SIT6 SIT5 SIT4 SIT3 SIT2 SIT1 SIT0 Bit Number Bit Mnemonic 7-0 SIT7:0 Description Status of interrupt by message object 0 - no interrupt. 1 - IT turned on. Reset when interrupt condition is cleared by user. SIT7:0 = 0b 0000 1001 -> IT’s on message objects 3 & 0. see Figure 33. Reset Value: 0000 0000b Table 48.
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T89C51CC01 Table 49. CANIE2 Register CANIE2 (S:C3h) CAN Enable Interrupt message object Registers 2 7 6 5 4 3 2 1 0 IECH 7 IECH 6 IECH 5 IECH 4 IECH 3 IECH 2 IECH 1 IECH 0 Bit Number Bit Mnemonic 7-0 IECH7:0 Description Enable interrupt by message object 0 - disable IT. 1 - enable IT. IECH7:0 = 0b 0000 1100 -> Enable IT’s of message objects 3 & 2. Reset Value: 0000 0000b Table 50.
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Table 51. CANBT2 Register CANBT2 (S:B5h) CAN Bit Timing Registers 2 7 6 5 4 3 2 1 0 - SJW 1 SJW 0 - PRS 2 PRS 1 PRS 0 - Bit Number Bit Mnemonic 7 - 6-5 SJW1:0 Description Reserved The value read from this bit is indeterminate. Do not set this bit. Re-synchronization jump width To compensate for phase shifts between clock oscillators of different bus controllers, the controller must re-synchronize on any relevant signal edge of the current transmission.
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T89C51CC01 Table 52. CANBT3 Register CANBT3 (S:B6h) CAN Bit Timing Registers 3 7 6 5 4 3 2 1 0 - PHS2 2 PHS2 1 PHS2 0 PHS1 2 PHS1 1 PHS1 0 SMP Bit Number Bit Mnemonic 7 - Description Reserved The value read from this bit is indeterminate. Do not set this bit. Phase segment 2 This phase is used to compensate for phase edge errors. This segment can be shortened by the re-synchronization jump width. 6-4 PHS2 2:0 Tphs2 = Tscl x (PHS2[2..
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Table 53. CANPAGE Register CANPAGE (S:B1h) CAN message object Page Register 7 6 5 4 3 2 1 0 CHNB 3 CHNB 2 CHNB 1 CHNB 0 AINC INDX2 INDX1 INDX0 Bit Number Bit Mnemonic 7-4 CHNB3:0 3 AINC 2-0 INDX2:0 Description Selection of message object number The available numbers are: 0 to 14 (see Figure 31). Auto increment of the index (active low) 0 - auto-increment of the index (default value). 1 - non-auto-increment of the index.
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T89C51CC01 Bit Number 3-0 Bit Mnemonic DLC3:0 Description Data length code Number of bytes in the data field of the message. The range of DLC is from 0 up to 8. This value is updated when a frame is received (data or remote frame). If the expected DLC differs from the incoming DLC, a warning appears in the CANSTCH register. No default value after reset Table 55.
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Bit Number Bit Mnemonic Description 1 FERR Form error The form error results from one or more violations of the fixed form in the following bit fields: CRC delimiter acknowledgment delimiter end_of_frame This flag can generate an interrupt. 0 AERR Acknowledgment error No detection of the dominant bit in the acknowledge slot. This flag can generate an interrupt. Note: See Figure 33. No default value after reset. Table 56. CANIDT1 Register for V2.0 part A CANIDT1 for V2.
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T89C51CC01 Table 58. CANIDT3 Register for V2.0 part A CANIDT3 for V2.0 part A (S:BEh) CAN Identifier Tag Registers 3 7 6 5 4 3 2 1 0 - - - - - - - - Bit Number Bit Mnemonic 7-0 - Description Reserved The values read from these bits are indeterminate. Do not set these bits. No default value after reset. CANIDT4 for V2.
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Table 60. CANIDT2 Register for V2.0 part B CANIDT2 for V2.0 part B (S:BDh) CAN Identifier Tag Registers 2 7 6 5 4 3 2 1 0 IDT 20 IDT 19 IDT 18 IDT 17 IDT 16 IDT 15 IDT 14 IDT 13 Bit Number Bit Mnemonic 7-0 IDT20:13 Description IDentifier tag value See Figure 37. No default value after reset. Table 61. CANIDT3 Register for V2.0 part B CANIDT3 for V2.
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T89C51CC01 Table 63. CANIDM1 Register for V2.0 part A CANIDM1 for V2.0 part A (S:C4h) CAN Identifier Mask Registers 1 7 6 5 4 3 2 1 0 IDMSK 10 IDMSK 9 IDMSK 8 IDMSK 7 IDMSK 6 IDMSK 5 IDMSK 4 IDMSK 3 Bit Number Bit Mnemonic 7-0 Description IDentifier mask value IDTMSK10 0 - comparison true forced. 1 - bit comparison enabled. :3 See Figure 37. No default value after reset. Table 64. CANIDM2 Register for V2.0 part A CANIDM2 for V2.
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Table 66. CANIDM4 Register for V2.0 part A CANIDM4 for V2.0 part A (S:C7h) CAN Identifier Mask Registers 4 7 6 5 4 3 2 1 0 - - - - - RTRMSK - IDEMSK Bit Number Bit Mnemonic 7-3 - 2 RTRMSK 1 - 0 IDEMSK Note: Description Reserved The values read from these bits are indeterminate. Do not set these bits. Remote transmission request mask value 0 - comparison true forced. 1 - bit comparison enabled. Reserved The value read from this bit is indeterminate. Do not set this bit.
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T89C51CC01 Table 68. CANIDM2 Register for V2.0 part B CANIDM2 for V2.0 part B (S:C5h) CAN Identifier Mask Registers 2 7 6 5 4 3 2 1 0 IDMSK 20 IDMSK 19 IDMSK 18 IDMSK 17 IDMSK 16 IDMSK 15 IDMSK 14 IDMSK 13 Bit Number Bit Mnemonic IDentifier mask value IDMSK20: 0 - comparison true forced. 1 - bit comparison enabled. 13 See Figure 37. 7-0 Note: Description The ID Mask is only used for reception. No default value after reset. Table 69. CANIDM3 Register for V2.0 part B CANIDM3 for V2.
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Table 70. CANIDM4 Register for V2.0 part B CANIDM4 for V2.0 part B (S:C7h) CAN Identifier Mask Registers 4 7 6 5 4 3 2 1 0 IDMSK 4 IDMSK 3 IDMSK 2 IDMSK 1 IDMSK 0 RTRMSK - IDEMSK Bit Number Bit Mnemonic IDentifier mask value 0 - comparison true forced. IDMSK4:0 1 - bit comparison enabled. See Figure 37. 7-3 2 RTRMSK 1 - 0 IDEMSK Note: Description Remote transmission request mask value 0 - comparison true forced. 1 - bit comparison enabled.
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T89C51CC01 Table 72. CANTCON Register CANTCON (S:A1h) CAN Timer ClockControl 7 6 5 4 3 2 1 0 TPRESC 7 TPRESC 6 TPRESC 5 TPRESC 4 TPRESC 3 TPRESC 2 TPRESC 1 TPRESC 0 Bit Number Bit Mnemonic 7-0 Description Timer Prescaler of CAN Timer TPRESC7: This register is a prescaler for the main timer upper counter range = 0 to 255. 0 See Figure 38. Reset Value: 00h Table 73.
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Table 75. CANSTMPH Register CANSTMPH (S:AFh Read Only) CAN Stamp Timer High 7 6 5 4 3 2 TIMSTMP 15 TIMSTMP 14 TIMSTMP 13 TIMSTMP 12 TIMSTMP 11 TIMSTMP 10 Bit Number Bit Mnemonic 7-0 1 0 TIMSTMP 9 TIMSTMP 8 Description TIMSTMP High byte of Time Stamp 15:8 See Figure 38. No default value after reset Table 76.
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T89C51CC01 Table 78. CANTTCL Register CANTTCL (S:A4h Read Only) CAN TTC Timer Low 7 6 5 4 3 2 1 0 TIMTTC 7 TIMTTC 6 TIMTTC 5 TIMTTC 4 TIMTTC 3 TIMTTC 2 TIMTTC 1 TIMTTC 0 Bit Number Bit Mnemonic 7-0 Description TIMTTC7: Low byte of TTC Timer 0 See Figure 38. Reset Value: 0000 0000b 107 Rev.
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16. Programmable Counter Array PCA The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accuracy. The PCA consists of a dedicated timer/counter which serves as the time base for an array of five compare/capture modules.
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T89C51CC01 Figure 40. PCA Timer/Counter To PCA modules FPca/6 overflow FPca / 2 CH T0 OVF It CL 16 bit up/down counter P1.2 CIDL WDTE CF CR CPS1 CPS0 ECF CMOD 0xD9 Idle CCF4 CCF3 CCF2 CCF1 CCF0 CCON 0xD8 The CMOD register includes three additional bits associated with the PCA. • The CIDL bit which allows the PCA to stop during idle mode. • The WDTE bit which enables or disables the watchdog function on module 4.
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Each module in the PCA has a special function register associated with it (CCAPM0 for module 0 ...). The CCAPM0:4 registers contain the bits that control the mode that each module will operate in. 16.3 PCA Interrupt • The ECCF bit enables the CCF flag in the CCON register to generate an interrupt when a match or compare occurs in the associated module. • The PWM bit enables the pulse width modulation mode.
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T89C51CC01 Figure 42. PCA Capture Mode PCA Counter CH (8bits) CL (8bits) CEXn n = 0, 4 CCAPnH CCAPnL PCA Interrupt Request CCFn CCON - 0CAPPnCAPNn000ECCFn 0 7 CCAPMn Register (n = 0, 4) 16.5 16-bit Software Timer Mode The PCA modules can be used as software timers by setting both the ECOM and MAT bits in the modules CCAPMn register.
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16.6 High Speed Output Mode In this mode the CEX output (on port 1) associated with the PCA module will toggle each time a match occurs between the PCA counter and the module’s capture registers. To activate this mode the TOG, MAT, and ECOM bits in the module’s CCAPMn SFR must be set. Figure 44.
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T89C51CC01 Figure 45. PCA PWM Mode CCAPnH CL rolls over from FFh TO 00h loads CCAPnH contents into CCAPnL CCAPnL “0” CL < CCAPnL CL (8 bits) 8-Bit Comparator CEX CL >= CCAPnL “1” 16.8 PCA Watchdog Timer ECOMn PWMn CCAPMn.6 CCAPMn.1 An on-board watchdog timer is available with the PCA to improve system reliability without increasing chip count. Watchdog timers are useful for systems that are sensitive to noise, power glitches, or electrostatic discharge.
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16.9 PCA Registers Table 79. CMOD Register CMOD (S:D8h) PCA Counter Mode Register 7 6 5 4 3 2 1 0 CIDL WDTE - - - CPS1 CPS0 ECF Bit Number Bit Mnemonic 7 CIDL 6 WDTE 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit. 3 - Reserved The value read from this bit is indeterminate. Do not set this bit.
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T89C51CC01 Table 80. CCON Register CCON (S:D8h) PCA Counter Control Register 7 6 5 4 3 2 1 0 CF CR - CCF4 CCF3 CCF2 CCF1 CCF0 Bit Number Bit Mnemonic 7 CF PCA Timer/Counter Overflow flag Set by hardware when the PCA Timer/Counter rolls over. This generates a PCA interrupt request if the ECF bit in CMOD register is set. Must be cleared by software. 6 CR PCA Timer/Counter Run Control bit Clear to turn the PCA Timer/Counter off. Set to turn the PCA Timer/Counter on.
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Table 81. CCAPnH Registers CCAP0H (S:FAh) CCAP1H (S:FBh) CCAP2H (S:FCh) CCAP3H (S:FDh) CCAP4H (S:FEh) PCA High Byte Compare/Capture Module n Register (n=0..4) 7 6 5 4 3 2 1 0 CCAPnH 7 CCAPnH 6 CCAPnH 5 CCAPnH 4 CCAPnH 3 CCAPnH 2 CCAPnH 1 CCAPnH 0 Bit Number Bit Mnemonic 7:0 CCAPnH 7:0 Description High byte of EWC-PCA comparison or capture values Reset Value = 0000 0000b Table 82.
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T89C51CC01 Table 83. CCAPMn Registers CCAPM0 (S:DAh) CCAPM1 (S:DBh) CCAPM2 (S:DCh) CCAPM3 (S:DDh) CCAPM4 (S:DEh) PCA Compare/Capture Module n Mode registers (n=0..4) 7 6 5 4 3 2 1 0 - ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn Bit Number Bit Mnemonic 7 - Description Reserved The Value read from this bit is indeterminate. Do not set this bit. 6 ECOMn Enable Compare Mode Module x bit Clear to disable the Compare function. Set to enable the Compare function.
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Table 84. CH Register CH (S:F9h) PCA Counter Register High value 7 6 5 4 3 2 1 0 CH 7 CH 6 CH 5 CH 4 CH 3 CH 2 CH 1 CH 0 Bit Number Bit Mnemonic 7:0 CH 7:0 Description High byte of Timer/Counter Reset Value = 0000 00000b Table 85. CL Register CL (S:E9h) PCA counter Register Low value 7 6 5 4 3 2 1 0 CL 7 CL 6 CL 5 CL 4 CL 3 CL 2 CL 1 CL 0 Bit Number Bit Mnemonic 7:0 CL0 7:0 Description Low byte of Timer/Counter Reset Value = 0000 00000b 118 T89C51CC01 Rev.
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T89C51CC01 17. Analog-to-Digital Converter (ADC) Th is se ction de scribe s the on -chip 10 bit an alog -to-d ig ita l c onv erte r of th e T89C51CC01. Eight ADC channels are available for sampling of the external sources AN0 to AN7. An analog multiplexer allows the single ADC converter to select one from the 8 ADC channels as ADC input voltage (ADCIN). ADCIN is converted by the 10 bitcascaded potentiometric ADC. Two kind of conversion are available: - Standard conversion (8 bits).
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Figure 46. ADC Description ADCON.5 ADCON.3 ADEN ADSST ADC Interrupt Request ADCON.4 ADEOC ADC CLOCK CONTROL EADC AN0/P1.0 000 AN1/P1.1 001 AN2/P1.2 010 AN3/P1.3 011 AN4/P1.4 100 AN5/P1.5 101 AN6/P1.6 110 AN7/P1.7 IEN1.1 ADCIN 8 ADDH 2 ADDL + SAR - AVSS Sample and Hold 111 10 R/2R DAC SCH2 SCH1 SCH0 ADCON.2 ADCON.1 ADCON.0 VAREF VAGND Figure 47 shows the timing diagram of a complete conversion.
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T89C51CC01 set, an interrupt occur when flag ADEOC is set (see Figure 49). Clear this flag for rearming the interrupt. The bits SCH0 to SCH2 in ADCON register are used for the analog input channel selection. Table 86. Selected Analog input 17.4 Voltage Conversion SCH2 SCH1 SCH0 Selected Analog input 0 0 0 AN0 0 0 1 AN1 0 1 0 AN2 0 1 1 AN3 1 0 0 AN4 1 0 1 AN5 1 1 0 AN6 1 1 1 AN7 When the ADCIN is equals to VAREF the ADC converts the signal to 3FFh (full scale).
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17.6 ADC Standby Mode When the ADC is not used, it is possible to set it in standby mode by clearing bit ADEN in ADCON register. In this mode its power dissipation is about 1uW. 17.7 IT ADC management An interrupt end-of-conversion will occurs when the bit ADEOC is activated and the bit EADC is set. For re-arming the interrupt the bit ADEOC must be cleared by software. Figure 49. ADC interrupt structure ADCI ADEOC ADCON.2 EADC IEN1.1 17.8 Routines examples 1. Configure P1.2 and P1.
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T89C51CC01 17.9 Registers Table 87. ADCF Register ADCF (S:F6h) ADC Configuration 7 6 5 4 3 2 1 0 CH 7 CH 6 CH 5 CH 4 CH 3 CH 2 CH 1 CH 0 Bit Number Bit Mnemonic 7-0 CH 0:7 Description Channel Configuration Set to use P1.x as ADC input. Clear to use P1.x as standart I/O port. Reset Value=0000 0000b Table 88.
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Table 89. ADCLK Register ADCLK (S:F2h) ADC Clock Prescaler 7 6 5 4 3 2 1 0 - - - PRS 4 PRS 3 PRS 2 PRS 1 PRS 0 Bit Number Bit Mnemonic 7-5 - 4-0 PRS4:0 Description Reserved The value read from these bits are indeterminate. Do not set these bits. Clock Prescaler fADC = fcpu clock/ (4 (or 2 in X2 mode)* (PRS +1)) Reset Value: XXX0 0000b Table 90.
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T89C51CC01 18. Interrupt System 18.1 Introduction The CAN Controller has a total of 10 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2), a serial port interrupt, a PCA, a CAN interrupt, a timer overrun interrupt and an ADC. These interrupts are shown below. Figure 55. Interrupt Control System INT0# 00 01 10 11 External Interrupt 0 Highest Priority Interrupts EX0 00 01 10 11 IEN0.0 Timer 0 ET0 00 01 10 11 IEN0.
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Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt Enable register. This register also contains a global disable bit which must be cleared to disable all the interrupts at the same time. Each interrupt source can also be individually programmed to one of four priority levels by setting or clearing a bit in the Interrupt Priority registers. The Table below shows the bit values and priority levels associated with each combination. Table 87.
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T89C51CC01 18.2 Registers Table 89. IEN0 Register IEN0 (S:A8h) Interrupt Enable Register 7 6 5 4 3 2 1 0 EA EC ET2 ES ET1 EX1 ET0 EX0 Bit Number Bit Mnemonic Description 7 EA Enable All interrupt bit Clear to disable all interrupts. Set to enable all interrupts. If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its interrupt enable bit. 6 EC PCA Interrupt Enable Clear to disable the PCA interrupt. Set to enable the PCA interrupt.
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Table 90. IEN1 Register IEN1 (S:E8h) Interrupt Enable Register 7 6 5 4 3 2 1 0 - - - - ETIM EADC ECAN Bit Number Bit Mnemonic 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit.
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T89C51CC01 Table 91. IPL0 Register IPL0 (S:B8h) Interrupt Enable Register 7 6 5 4 3 2 1 0 - PPC PT2 PS PT1 PX1 PT0 PX0 Bit Number Bit Mnemonic 7 - 6 PPC PCA Interrupt Priority bit Refer to PPCH for priority level 5 PT2 Timer 2 overflow interrupt Priority bit Refer to PT2H for priority level. 4 PS Serial port Priority bit Refer to PSH for priority level. 3 PT1 Timer 1 overflow interrupt Priority bit Refer to PT1H for priority level.
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Table 92. IPL1 Register IPL1 (S:F8h) Interrupt Priority Low Register 1 7 6 5 4 3 2 1 0 - - - - POVRL PADCL PCANL Bit Number Bit Mnemonic 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit.
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T89C51CC01 Table 93. IPL0 Register IPH0 (B7h) Interrupt High Priority Register 7 6 5 4 3 2 1 0 - PPCH PT2H PSH PT1H PX1H PT0H PX0H Bit Number Bit Mnemonic 7 - 6 5 4 3 2 1 0 PPCH Description Reserved The value read from this bit is indeterminate. Do not set this bit.
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Table 94. IPH1 Register IPH1 (S:FFh) Interrupt high priority Register 1 7 6 5 4 - - - - Bit Number Bit Mnemonic 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit.
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T89C51CC01 19. Electrical Characteristics 19.1 Absolute Maximum Ratings (1) Note: Ambiant Temperature Under Bias: I = industrial.................................................-40°C to 85°C Storage Temperature ............................-65°C to + 150°C Voltage on VCC from V SS..........................................-0.5 V to + 6V Voltage on Any Pin from VSS............-0.5 V to VCC + 0.2 V Stresses at or above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
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Symbol Parameter ITL Logical 1 to 0 Transition Current, ports 1, 2, 3 and 4 CIO Capacitance of I/O Buffer IPD Power Down Current Min Typ(5) Max -650 160 Unit Test Conditions µA Vin = 2.0 V 10 pF Fc = 1 MHz TA = 25°C 350 µA 4.5V < VCC < 5.5V(3) Power Supply Current ICC ICCOP = 0.7 Freq (MHz) + 3 mA ICCIDLE = 0.6 Freq (MHz) + 2 mA Notes: 134 1. Operating ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 61.), VIL = VSS + 0.
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T89C51CC01 Figure 58. ICC Test Condition, Active Mode VCC ICC VCC P0 VCC RST (NC) CLOCK SIGNAL VCC EA XTAL2 XTAL1 VSS All other pins are disconnected. Figure 59. ICC Test Condition, Idle Mode VCC ICC VCC VCC P0 RST EA XTAL2 XTAL1 VSS (NC) CLOCK SIGNAL All other pins are disconnected. Figure 60. ICC Test Condition, Power-Down Mode VCC ICC VCC VCC P0 RST (NC) EA XTAL2 XTAL1 VSS All other pins are disconnected. 135 Rev.
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Figure 61. Clock Signal Waveform for ICC Tests in Active and Idle Modes VCC-0.5V 0.45V TCLCH TCHCL TCLCH = TCHCL = 5ns. 0.7VCC 0.2VCC-0.1 19.3 DC Parameters for A/D Converter Table 94. DC Parameters for AD Converter in Precision conversion Symbol Parameter Min Typ(1) Unit Vref + 0.2 V 24 KO hm 3.
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T89C51CC01 19.4.2 External Program Memory Characteristics Table 95. Symbol Description Symbol T Parameter Oscillator clock period TLHLL ALE pulse width TAVLL Address Valid to ALE TLLAX Address Hold After ALE TLLIV ALE to Valid Instruction In TLLPL ALE to PSEN TPLPH PSEN Pulse Width TPLIV PSEN to Valid Instruction In TPXIX Input Instruction Hold After PSEN TPXIZ Input Instruction Float After PSEN TAVIV Address to Valid Instruction In TPLAZ PSEN Low to Address Float Table 96.
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Table 97. AC Parameters for a Variable Clock Symbol Type Standard Clock X2 Clock X parameter Units TLHLL Min 2T-x T-x 10 ns TAVLL Min T-x 0.5 T - x 15 ns TLLAX Min T-x 0.5 T - x 15 ns TLLIV Max 4T-x 2T-x 30 ns TLLPL Min T-x 0.5 T - x 10 ns TPLPH Min 3T-x 1.5 T - x 20 ns TPLIV Max 3T-x 1.5 T - x 40 ns TPXIX Min x x 0 ns TPXIZ Max T-x 0.5 T - x 7 ns TAVIV Max 5T-x 2.5 T - x 40 ns TPLAZ Max x x 10 ns 19.4.
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T89C51CC01 19.4.4 External Data Memory Characteristics Table 98.
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Table 100. AC Parameters for a Variable Clock Symbol Type Standard Clock X2 Clock X parameter Units TRLRH Min 6T-x 3T-x 20 ns TWLWH Min 6T-x 3T-x 20 ns TRLDV Max 5T-x 2.5 T - x 25 ns TRHDX Min x x 0 ns TRHDZ Max 2T-x T-x 20 ns TLLDV Max 8T-x 4T -x 40 ns TAVDV Max 9T-x 4.5 T - x 60 ns TLLWL Min 3T-x 1.5 T - x 25 ns TLLWL Max 3T+x 1.5 T + x 25 ns TAVWL Min 4T-x 2T-x 25 ns TQVWX Min T-x 0.5 T - x 15 ns TQVWH Min 7T-x 3.
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T89C51CC01 19.4.6 External Data Memory Read Cycle TWHLH TLLDV ALE PSEN TLLWL TRLRH RD TRHDZ TAVDV TLLAX PORT 0 TRHDX A0-A7 DATA IN TRLAZ TAVWL PORT 2 19.4.7 Serial Port Timing Shift Register Mode ADDRESS OR SFR-P2 ADDRESS A8-A15 OR SFR P2 Table 101.
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Table 103. AC Parameters for a Variable Clock Symbol Type Standard Clock X2 Clock X parameter for -M range TXLXL Min 12 T 6T TQVHX Min 10 T - x 5T-x 50 ns TXHQX Min 2T-x T-x 20 ns TXHDX Min x x 0 ns TXHDV Max 10 T - x 5 T- x 133 ns Units ns 19.4.8 Shift Register Timing Waveforms 0 INSTRUCTION 1 2 3 4 5 6 7 8 ALE TXLXL CLOCK TXHQX TQVXH 0 OUTPUT DATA 1 2 INPUT DATA 4 5 6 VALID VALID VALID SET TI VALID VALID VALID VALID VALID SET RI CLEAR RI 19.4.
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T89C51CC01 19.4.11 AC Testing Input/Output Waveforms VCC -0.5 V INPUT/OUTPUT 0.45 V 0.2 VCC + 0.9 0.2 VCC - 0.1 AC inputs during testing are driven at VCC - 0.5 for a logic “1” and 0.45V for a logic “0”. Timing measurement are made at VIH min for a logic “1” and VIL max for a logic “0”. 19.4.12 Float Waveforms FLOAT VOH - 0.1 V VOL + 0.1 V VLOAD VLOAD + 0.1 V VLOAD - 0.
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INTERNAL CLOCK STATE4 STATE5 STATE6 STATE1 STATE2 STATE3 STATE4 STATE5 P1 P1 P1 P1 P1 P1 P1 P1 P2 P2 P2 P2 P2 P2 P2 P2 XTAL2 ALE THESE SIGNALS ARE NOT ACTIVATED DURING THE EXECUTION OF A MOVX INSTRUCTION EXTERNAL PROGRAM MEMORY FETCH PSEN P0 DATA SAMPLED PCL OUT DATA SAMPLED FLOAT P2 (EXT) PCL OUT FLOAT DATA SAMPLED PCL OUT FLOAT INDICATES ADDRESS TRANSITIONS READ CYCLE RD PCL OUT (IF PROGRAM MEMORY IS EXTERNAL) DPL OR Rt OUT P0 P2 DATA SAMPLED FLOAT INDICATES DPH OR
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T89C51CC01 19.5.14 Flash Memory Table 105. Timing Symbol Definitions Signals Conditions S(Hardware condition) PSEN#,EA L Low R RST V Valid B FBUSY flag X No Longer Valid Table 106. Memory AC Timing VDD= 5 V +/- 10% , TA= -40 to +85°C Symbol Parameter Min Typ Max Unit TSVRL Input PSEN# Valid to RST Edge 50 ns TRLSX Input PSEN# Hold after RST Edge 50 ns TBHBL FLASH Internal Busy (Programming) Time 10 ms Figure 62.
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20. Ordering Information Table 106. Possible order entries 146 Part Number Boot Loader Temperature Range Package Packing T89C51CC01UA-7CTIM UART Industrial CA-BGA Tray T89C51CC01UA-RLTIM UART Industrial VQFP44 Tray T89C51CC01UA-SLSIM UART Industrial PLCC44 Stick T89C51CC01CA-7CTIM CAN Industrial CA-BGA Tray T89C51CC01CA-RLTIM CAN Industrial VQFP44 Tray T89C51CC01CA-SLSIM CAN Industrial PLC44 Stick T89C51CC01 Rev.
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T89C51CC01 Table of Contents 1. Features .......................................................................................................... 1 2. Description ....................................................................................................... 2 3. Block Diagram ................................................................................................. 2 4. Pin Configuration ............................................................................................. 3 4.
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14.1 WatchDog Programming ......................................................................... 68 14.2 WatchDog Timer during Power down mode and Idle .............................. 68 15. Atmel CAN Controller ..................................................................................... 71 15.1 CAN Controller Description ..................................................................... 71 15.2 CAN Controller Mailbox and Registers Organization .............................. 72 15.
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Atmel Headquarters Atmel Operations Corporate Headquarters Memory 2325 Orchard Parkway San Jose, CA 95131 TEL (408) 441-0311 FAX (408) 487-2600 Europe Atmel SarL Route des Arsenaux 41 Casa Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Asia Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Japan Atmel Japan K.K. 9F, Tonetsu Shinkawa Bldg.