User Manual

T89C51AC2

Rev. B – 19-Dec-01

14. WatchDog Timer T89C51AC2 contains a powerful programm able hardw are WatchDog T im er (WDT) that

automat ically resets the chip if it s oftware f ails to reset the WDT before the selected time

interval has elapsed. It permits large Time-Out ranking from 16ms to 2s @Fosc =

12MHz in X1 mode.

This WDT consists of a 14-bit counter plus a 7-bit pro grammable counte r, a Wa tchDog

Timer reset regist er (WDTRST) an d a WatchDog Tim er program ming (WDTPRG) regis-

ter. When exiting reset, the WDT is -by default- disable.

To enable the WDT, the user has to write the sequence 1EH and E1H into W DTRST

ment every m achine cycle while the oscillator is run ning and there is n o way to disable

the WDT except through reset (either hardware reset or WDT ov erflow reset). When

WDT overflows, it will generate an output RE SET pulse at the RST pin. The RESET

pulse duration is 96xT

OSC

,whereT

OS C

=1/F

OSC

. To make the best use of the WDT, it

shou ld be serviced in those sections of c ode that will periodically be executed within t he

time required to prevent a WDT reset

Note: When the watchdog is enable it is impossible to change its period.

Figure 29. WatchDog Timer

÷ 6

÷ PS

CPU and Peripheral

Clock

Fwd

CLOCK

WDTPRG

RESET

Decoder

Control

WDTRST

Enable

14-bit COUNTER

7-bit C OUNTER

Outputs

Fwd Clock

RESET